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refactor: refactor APB4 and AXI4 references in RTL and test files

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- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.
This commit is contained in:
maksyuki committed 2026-08-17 12:38:43 +08:00
1 parent 662488d385
commit 6bb5dc2344
54 files changed
+1574 -1840
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tests/rtl/axi4_interconnect_tb.sv
+23 -23
View File
@@ -44,29 +44,29 @@ module axi4_interconnect_tb;
.NumMasters(NumMasters),
.NumTargets(NumTargets)
) u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.masters (masters),
.targets (targets),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
.fault_addr_o (fault_addr_o),
.fault_wstrb_o (fault_wstrb_o),
.fault_reserved_o (fault_reserved_o),
.fault_access_o (fault_access_o),
.fault_master_o (fault_master_o),
.fault_code_o (fault_code_o),
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_apb4_wait_o (),
.perf_apb_wait_o (),
.perf_sdram_wait_o(),
.perf_psram_wait_o(),
.perf_flash_wait_o()
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.masters (masters),
.targets (targets),
.user_bus_enable_i (1'b1),
.user_bus_idle_o (user_bus_idle_o),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
.fault_addr_o (fault_addr_o),
.fault_wstrb_o (fault_wstrb_o),
.fault_reserved_o (fault_reserved_o),
.fault_access_o (fault_access_o),
.fault_master_o (fault_master_o),
.fault_code_o (fault_code_o),
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_apb4_periph_wait_o(),
.perf_apb4_system_wait_o(),
.perf_sdram_wait_o (),
.perf_psram_wait_o (),
.perf_flash_wait_o ()
);
for (genvar target = 0; target < NumTargets; target++) begin : GEN_TARGETS
tests/rtl/rib_bus_tb.sv
+26 -26
View File
@@ -67,32 +67,32 @@ module rib_bus_tb;
assign apb_rib.rsp_last = 1'b1;
rib_bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_rib (mgmt_rib),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_rib (apb_rib),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
.fault_addr_o (),
.fault_wstrb_o (),
.fault_reserved_o (),
.fault_access_o (),
.fault_master_o (),
.fault_code_o (fault_code_o),
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_apb4_wait_o (),
.perf_apb_wait_o (),
.perf_sdram_wait_o(),
.perf_psram_wait_o(),
.perf_flash_wait_o()
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_rib (mgmt_rib),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i (1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_rib (apb_rib),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
.fault_addr_o (),
.fault_wstrb_o (),
.fault_reserved_o (),
.fault_access_o (),
.fault_master_o (),
.fault_code_o (fault_code_o),
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_apb4_periph_wait_o(),
.perf_apb4_system_wait_o(),
.perf_sdram_wait_o (),
.perf_psram_wait_o (),
.perf_flash_wait_o ()
);
task automatic issue_read(input logic [31:0] address, input logic [1:0] length,
tests/rtl/soc_irq_topology_tb.sv
+16 -16
View File
@@ -3,9 +3,9 @@
`include "soc_irq_config.svh"
module soc_irq_topology_tb;
logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
logic [ `SOC_IRQ_APB4_WIDTH-1:0] s_apb4_irq;
logic [ `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
logic [ `SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] s_apb4_periph_irq;
logic [`SOC_IRQ_APB4_SYSTEM_WIDTH-1:0] s_apb4_system_irq;
`include "soc_irq_wiring.svh"
@@ -19,30 +19,30 @@ module soc_irq_topology_tb;
endtask
initial begin
s_apb4_irq = '0;
s_apb_irq = '0;
s_apb4_periph_irq = '0;
s_apb4_system_irq = '0;
expect_irq('0);
for (int bit_index = 0; bit_index < 10; bit_index++) begin
s_apb4_irq = '0;
s_apb4_irq[bit_index] = 1'b1;
s_apb_irq = '0;
s_apb4_periph_irq = '0;
s_apb4_periph_irq[bit_index] = 1'b1;
s_apb4_system_irq = '0;
expect_irq(32'd1 << bit_index);
end
for (int bit_index = 10; bit_index < `SOC_IRQ_APB4_WIDTH; bit_index++) begin
s_apb4_irq = '0;
s_apb4_irq[bit_index] = 1'b1;
for (int bit_index = 10; bit_index < `SOC_IRQ_APB4_PERIPH_WIDTH; bit_index++) begin
s_apb4_periph_irq = '0;
s_apb4_periph_irq[bit_index] = 1'b1;
case (bit_index)
13: expect_irq(32'd1 << 15);
default: expect_irq(32'd1 << (bit_index + 7));
endcase
end
for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
s_apb4_irq = '0;
s_apb_irq = '0;
s_apb_irq[bit_index] = 1'b1;
for (int bit_index = 0; bit_index < `SOC_IRQ_APB4_SYSTEM_WIDTH; bit_index++) begin
s_apb4_periph_irq = '0;
s_apb4_system_irq = '0;
s_apb4_system_irq[bit_index] = 1'b1;
case (bit_index)
0: expect_irq(32'd1 << 11);
1: expect_irq(32'd1 << 12);
@@ -53,7 +53,7 @@ module soc_irq_topology_tb;
endcase
end
s_apb_irq = '0;
s_apb4_system_irq = '0;
expect_irq('0);
if (s_irq[10] !== 1'b0) begin
$fatal(1, "removed core IRQ bit is not low: IRQ10=%b", s_irq[10]);
tests/rtl/sysctrl_tb.sv
+25 -25
View File
@@ -73,31 +73,31 @@ module sysctrl_tb;
logic [31:0] read_data;
initial begin
apb4.psel = 1'b0;
apb4.paddr = '0;
apb4.pwdata = '0;
apb4.pstrb = '0;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
sysctrl.fault_code_i = `RIB_RESP_RESERVED;
sysctrl.perf_mgmt_wait_i = 64'd11;
sysctrl.perf_user_wait_i = 64'd12;
sysctrl.perf_dma_wait_i = 64'd13;
sysctrl.perf_apb4_wait_i = 64'd14;
sysctrl.perf_apb_wait_i = 64'd15;
sysctrl.perf_sdram_wait_i = 64'd16;
sysctrl.perf_psram_wait_i = 64'd17;
sysctrl.perf_flash_wait_i = 64'd18;
sysctrl.rtc_wake_i = 1'b0;
pll_ctrl.req_ready_i = 1'b1;
pll_ctrl.rsp_active_sel_i = '0;
pll_ctrl.rsp_active_valid_i = 1'b0;
pll_ctrl.rsp_safe_clk_i = 1'b1;
pll_ctrl.rsp_pll_lock_i = 1'b0;
pll_ctrl.rsp_error_i = '0;
pll_ctrl.rsp_valid_i = 1'b0;
pll_ctrl.capable_i = 1'b0;
apb4.psel = 1'b0;
apb4.paddr = '0;
apb4.pwdata = '0;
apb4.pstrb = '0;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
sysctrl.fault_code_i = `RIB_RESP_RESERVED;
sysctrl.perf_mgmt_wait_i = 64'd11;
sysctrl.perf_user_wait_i = 64'd12;
sysctrl.perf_dma_wait_i = 64'd13;
sysctrl.perf_apb4_periph_wait_i = 64'd14;
sysctrl.perf_apb4_system_wait_i = 64'd15;
sysctrl.perf_sdram_wait_i = 64'd16;
sysctrl.perf_psram_wait_i = 64'd17;
sysctrl.perf_flash_wait_i = 64'd18;
sysctrl.rtc_wake_i = 1'b0;
pll_ctrl.req_ready_i = 1'b1;
pll_ctrl.rsp_active_sel_i = '0;
pll_ctrl.rsp_active_valid_i = 1'b0;
pll_ctrl.rsp_safe_clk_i = 1'b1;
pll_ctrl.rsp_pll_lock_i = 1'b0;
pll_ctrl.rsp_error_i = '0;
pll_ctrl.rsp_valid_i = 1'b0;
pll_ctrl.capable_i = 1'b0;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;