fix: tier unused irq to constant value

rtl/retrosoc.v

@@ -215,18 +215,19 @@ module retrosoc #(
   wire        s_irq_spi_mst;
   wire        s_irq_tim0;
 
-  assign s_irq[2:0] = 3'd0;
-  assign s_irq[3]   = s_irq_stall;
-  assign s_irq[4]   = s_irq_uart;
-  assign s_irq[5]   = irq_pin_i;
-  assign s_irq[6]   = irq_spi_i;
-  assign s_irq[7]   = s_irq_7;
-  assign s_irq[8]   = s_irq_8;
-  assign s_irq[9]   = 1'd0;
-  assign s_irq[10]  = 1'd0;
-  assign s_irq[11]  = s_irq_i2c;
-  assign s_irq[12]  = s_irq_spi_mst;
-  assign s_irq[13]  = s_irq_tim0;
+  assign s_irq[2:0]   = 3'd0;
+  assign s_irq[3]     = s_irq_stall;
+  assign s_irq[4]     = s_irq_uart;
+  assign s_irq[5]     = irq_pin_i;
+  assign s_irq[6]     = irq_spi_i;
+  assign s_irq[7]     = s_irq_7;
+  assign s_irq[8]     = s_irq_8;
+  assign s_irq[9]     = 1'd0;
+  assign s_irq[10]    = 1'd0;
+  assign s_irq[11]    = s_irq_i2c;
+  assign s_irq[12]    = s_irq_spi_mst;
+  assign s_irq[13]    = s_irq_tim0;
+  assign s_irq[31:14] = 18'd0;
 
   wire        s_mem_valid;
   wire        s_mem_instr;
@@ -588,4 +589,4 @@ endmodule
 
 //   assign rdata1 = regs[raddr1[4:0]];
 //   assign rdata2 = regs[raddr2[4:0]];
-// endmodule
+// endmodule

rtl/retrosoc_asic.v

@@ -193,7 +193,8 @@ module retrosoc_asic (
   // reset assignment. "s_rst_n_i" comes from button, while "s_hk_rst"
   // comes from standalone SPI (and is normally zero unless activated from the SPI).
   assign s_clk   = s_hk_pll_bypass ? s_xclk_i_buf : s_pll_clk_buf;
-  assign s_rst_n = s_rst_n_i & ~s_hk_rst;
+//   assign s_rst_n = s_rst_n_i & ~s_hk_rst;
+  assign s_rst_n = s_rst_n_i;
   retrosoc u_retrosoc (
       .clk_i                    (s_clk),
       .rst_n_i                  (s_rst_n),

rtl/retrosoc_tb.v

@@ -22,25 +22,22 @@
 module retrosoc_tb;
   // localparam ser_half_period = 53;
   localparam ser_half_period = 26;
-  event       ser_sample;
+  event ser_sample;
 
-  reg         r_clk;
-  reg   [5:0] r_rst_cnt = 0;
-  wire s_uart_rx, s_uart_tx;
-  wire s_flash_csb;
-  wire s_flash_clk;
-  wire s_flash_io0;
-  wire s_flash_io1;
-  wire s_flash_io2;
-  wire s_flash_io3;
+  reg   r_clk;
+  reg   s_rst_n;
+  wire  s_uart_rx;
+  wire  s_flash_csb;
+  wire  s_flash_clk;
+  wire  s_flash_io0;
+  wire  s_flash_io1;
+  wire  s_flash_io2;
+  wire  s_flash_io3;
+  wire  s_i2c_sda_io;
+  wire  s_i2c_scl_io;
 
   // always #5 r_clk = (r_clk === 1'b0);  // 100M
   always #10 r_clk = (r_clk === 1'b0);  // 50M
-  wire s_rst_n = &r_rst_cnt;
-
-  always @(posedge r_clk) begin
-    r_rst_cnt <= r_rst_cnt + !s_rst_n;
-  end
 
   retrosoc_asic u_retrosoc_asic (
       .xi_i_pad         (r_clk),
@@ -62,9 +59,9 @@ module retrosoc_tb;
       .flash_io2_io_pad (s_flash_io2),
       .flash_io3_io_pad (s_flash_io3),
       .uart_tx_o_pad    (s_uart_tx),
-      .uart_rx_i_pad    (s_uart_rx),
-      .i2c_sda_io_pad   (),
-      .i2c_scl_io_pad   (),
+      .uart_rx_i_pad    (1'b0),
+      .i2c_sda_io_pad   (s_i2c_sda_io),
+      .i2c_scl_io_pad   (s_i2c_scl_io),
       .gpio_0_o_pad     (),
       .gpio_1_o_pad     (),
       .gpio_2_o_pad     (),
@@ -93,6 +90,15 @@ module retrosoc_tb;
       .io3(s_flash_io3)
   );
 
+  i2c_slave u_i2c_slave (
+      .scl(s_i2c_scl_io),
+      .sda(s_i2c_sda_io)
+  );
+
+  // Testbench pullups on SDA, SCL lines
+  pullup i2c_scl_up (s_i2c_scl_io);
+  pullup i2c_sda_up (s_i2c_sda_io);
+
   reg [7:0] buffer;
   always begin
     @(negedge s_uart_tx);
@@ -123,6 +129,14 @@ module retrosoc_tb;
       );
   end
 
+  initial begin
+    s_rst_n = 1;
+    #60;
+    s_rst_n = 0;
+    #100;
+    s_rst_n = 1;
+  end
+
   initial begin
     if ($test$plusargs("behv_wave")) begin
       $dumpfile("retrosoc_tb.fst");

tech/tc_io.v

@@ -5,7 +5,8 @@ module ihp_io_xtl_pad (
     output clk
 );
 
-  assign clk = en ? xi_pad : 1'b0;
+  assign clk    = en ? xi_pad : 1'b0;
+  assign xo_pad = xi_pad;
 endmodule
 
 module ihp_io_tri_pad (