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feat: chg flash addr to cust spi flash ctrl

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maksyuki committed 2025-02-06 15:40:15 +08:00
1 parent 32b0597aae
commit a6ef598aa2
6 files changed
+19 -21
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crt/sections.lds
+1 -1
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@@ -1,7 +1,7 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x00100000, LENGTH = 0x1000000 /* entire flash, 16 MiB */
FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 0x1000000 /* entire flash, 16 MiB */
/*FLASH (rx) : ORIGIN = 0x00100000, LENGTH = 0x400000 entire flash, 4 MiB*/
RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x10000 /* 64KB */
}
rtl/ip/axil_ip_wrapper.v
+1 -1
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@@ -215,7 +215,7 @@ module axil_ip_wrapper (
.c_apb_num_slaves(APB_SLAVES_NUM),
.memory_regions1 (MEM_REGIONS1),
.memory_regions2 (MEM_REGIONS2),
.timeout_val (1),
.timeout_val (32'hFFFF_FFFF),
.APB_Protocol (4)
) u_axi_apb_bridge (
.s_axi_clk (clk_i),
rtl/ip/cust/axil2apb/apb_master.v
+7 -3
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@@ -27,6 +27,10 @@ module apb_master #(
reg [1:0] state;
// for select ongoing slave
wire s_filter_pready = |(SSEL & PREADY);
// PREADY & SSEL
// 0111 & 1000 = 0000
always @(posedge PCLK) begin
if (!PRESETn) state <= Idle;
if (state == Idle) begin
@@ -34,9 +38,9 @@ module apb_master #(
else state <= Idle;
end else if (state == Setup) state <= Access;
else if (state == Access) begin
if (PREADY && STREQ) state <= Setup;
else if (PREADY && ~STREQ) state <= Idle;
else if (~PREADY) state <= Access;
if (s_filter_pready && STREQ) state <= Setup;
else if (s_filter_pready && ~STREQ) state <= Idle;
else if (~s_filter_pready) state <= Access;
else state <= Idle;
end else state <= Idle;
rtl/ip/cust/axil2apb/axi_apb_bridge.v
-6
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@@ -1,9 +1,3 @@
/*
`include "apb_master.v"
`include "address_decoder.v"
`include "read_data_mux.v"
`include "flop.v"
*/
module axi_apb_bridge #(
parameter c_apb_num_slaves = 1,
rtl/retrosoc.v
+2 -2
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@@ -35,8 +35,8 @@
module retrosoc #(
parameter integer MEM_WORDS = 16384,
parameter [31:0] STACKADDR = (4 * MEM_WORDS), // end of memory
// parameter [31:0] PROGADDR_RESET = 32'h3000_0000, // flash
parameter [31:0] PROGADDR_RESET = 32'h0010_0000, // flash
parameter [31:0] PROGADDR_RESET = 32'h3000_0000, // flash
// parameter [31:0] PROGADDR_RESET = 32'h0010_0000, // flash
parameter PSRAM_NUM = 4
) (
input clk_i,
rtl/retrosoc_tb.v
+8 -8
View File
@@ -132,14 +132,14 @@ module retrosoc_tb;
// .Vpp_W_DQ2()
// );
spiflash u_spiflash (
.csb(s_flash_csb),
.clk(s_flash_clk),
.io0(s_flash_io0), // MOSI
.io1(s_flash_io1), // MISO
.io2(s_flash_io2),
.io3(s_flash_io3)
);
// spiflash u_spiflash (
// .csb(s_flash_csb),
// .clk(s_flash_clk),
// .io0(s_flash_io0), // MOSI
// .io1(s_flash_io1), // MISO
// .io2(s_flash_io2),
// .io3(s_flash_io3)
// );
N25Qxxx u_N25Qxxx (
.C_ (s_cust_spfs_clk_o),