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feat(hp): add the GF180 SRAM macro path to the OpenC906 wrappers

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Add a PDK_GF180+HAVE_SRAM_MACRO (without PDK_BEHAV) branch to each of the
eight aq_spsram_* overrides, tiling the 8-bit GF180 macros
(sram{64,128,256,512}x8m8wm1, per-bit active-low WEN, matching polarity so
no inversion is needed): 512x8 tiles with registered read-mux depth
stacking for 1024x16/2048x32/1024x64, width stacks of depth-exact 256x8
and 64x8 tiles for 256x59/64x58/64x88/64x98 (partial top tiles tie unused
WEN bits inactive), and a single exact 128x8 tile for the dirty array.
VDD/VSS follow the tc_sram.sv GF180 convention.

The GF180 CI profile (HAVE_HP=YES, HAVE_SRAM_MACRO=YES, PDK_BEHAV unset)
now compiles the macro path automatically. Behavioral, IHP130, and ICS55
paths are bit-identical. SKY130 intentionally stays behavioral: the locked
OpenRAM macro offers only byte-granular wmask0 while six of the eight C906
arrays require per-bit writes (BHT one-hot, 29/44/48-bit field groups,
single-bit dirty updates).

Evidence: directed 8-wrapper equivalence TB and the MEM_INTF adaptation
pass on the GF180 path; the gf180 boot testbench and the GF180 SoC
hp-smoke-sim both pass (SIM_TEST_PASS code=0, 3,644,186 cycles, identical
to every other macro mode).
This commit is contained in:
maksyuki committed 2026-10-15 15:54:42 +08:00
1 parent e5819d0a27
commit a8c897d475
8 files changed
+481 -20
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rtl/mini/ip_overrides/aq_spsram_1024x16.v
+64 -1
View File
@@ -11,7 +11,11 @@
// bits are used and the upper mask bits are tied off so they are never
// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
// exact-geometry ics55_ecos_sram_1024x16_m8 macro replaces it directly
// (identical active-low polarity, no stacking or padding). Every other
// (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, GF180
// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (two deep selected by
// A[9] with a registered read mux, times two wide; the repo-owned functional
// models live in rtl/tech/gf180_sram_sim_cells.sv). Every other
// configuration keeps the upstream behavioral aq_f_spsram_1024x16 instance
// byte-identical. Keep in sync when the lock revision changes.
@@ -90,6 +94,14 @@ parameter WE_WIDTH = 16;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_1024X16_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_1024X16_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -137,6 +149,53 @@ ics55_ecos_sram_1024x16_m8 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_1024X16_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Four 512x8 tiles: two deep selected by A[9] with the bank select
// registered on read transactions, times two wide.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [31:0] s_q;
reg s_rd_sel_q;
genvar g_d;
genvar g_w;
always @(posedge CLK) begin
if (!CEN && GWEN) begin
s_rd_sel_q <= A[9];
end
end
assign Q = s_rd_sel_q ? s_q[31:16] : s_q[15:0];
generate
for (g_d = 0; g_d < 2; g_d = g_d + 1) begin : gen_depth
for (g_w = 0; g_w < 2; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (~(~CEN & (A[9] == g_d)) ),
.GWEN (GWEN ),
.WEN (WEN[g_w*8 +: 8] ),
.A (A[8:0] ),
.D (D[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_d*16 + g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_d*16 + g_w*8 +: 8] )
`endif
);
end
end
endgenerate
`else
//********************************************************
//* FPGA memory *
@@ -161,6 +220,10 @@ aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 (
`undef _AQ_SPSRAM_1024X16_ICS55_
`endif
`ifdef _AQ_SPSRAM_1024X16_GF180_
`undef _AQ_SPSRAM_1024X16_GF180_
`endif
// &Instance("aq_tsmc_spsram_1024x16"); @49
// &Instance("aq_umc_spsram_1024x16"); @61
rtl/mini/ip_overrides/aq_spsram_1024x64.v
+64 -1
View File
@@ -11,7 +11,11 @@
// stack: one macro holds the low 32 bits, the other the high 32 bits (manual
// section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without
// PDK_BEHAV, the exact-geometry ics55_ecos_sram_1024x64_m8 macro replaces it
// directly (identical active-low polarity, no stacking or padding). Every
// directly (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, GF180
// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (two deep selected by
// A[9] with a registered read mux, times eight wide; the repo-owned
// functional models live in rtl/tech/gf180_sram_sim_cells.sv). Every
// other configuration keeps the upstream behavioral aq_f_spsram_1024x64
// instance byte-identical. Keep in sync when the lock revision changes.
@@ -90,6 +94,14 @@ parameter WE_WIDTH = 64;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_1024X64_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_1024X64_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -156,6 +168,53 @@ ics55_ecos_sram_1024x64_m8 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_1024X64_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Sixteen 512x8 tiles: two deep selected by A[9] with the bank select
// registered on read transactions, times eight wide.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [127:0] s_q;
reg s_rd_sel_q;
genvar g_d;
genvar g_w;
always @(posedge CLK) begin
if (!CEN && GWEN) begin
s_rd_sel_q <= A[9];
end
end
assign Q = s_q[s_rd_sel_q*64 +: 64];
generate
for (g_d = 0; g_d < 2; g_d = g_d + 1) begin : gen_depth
for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (~(~CEN & (A[9] == g_d)) ),
.GWEN (GWEN ),
.WEN (WEN[g_w*8 +: 8] ),
.A (A[8:0] ),
.D (D[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_d*64 + g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_d*64 + g_w*8 +: 8] )
`endif
);
end
end
endgenerate
`else
// //********************************************************
// //* FPGA memory *
@@ -180,6 +239,10 @@ aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 (
`undef _AQ_SPSRAM_1024X64_ICS55_
`endif
`ifdef _AQ_SPSRAM_1024X64_GF180_
`undef _AQ_SPSRAM_1024X64_GF180_
`endif
// &Instance("aq_umc_spsram_1024x64"); @49
// &Instance("aq_tsmc_spsram_1024x64"); @55
// &ModuleEnd; @58
rtl/mini/ip_overrides/aq_spsram_128x8.v
+47 -3
View File
@@ -13,9 +13,13 @@
// mux uses the bank select registered on read transactions (manual section
// 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV,
// the exact-geometry ics55_ecos_sram_128x8_m8 macro replaces it directly
// (identical active-low polarity, no stacking or padding). Every other
// configuration keeps the upstream behavioral aq_f_spsram_128x8 instance
// byte-identical. Keep in sync when the lock revision changes.
// (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, one exact-geometry GF180
// gf180mcu_fd_ip_sram__sram128x8m8wm1 tile replaces it directly (the
// repo-owned functional models live in rtl/tech/gf180_sram_sim_cells.sv).
// Every other configuration keeps the upstream behavioral
// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock
// revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -92,6 +96,14 @@ parameter WE_WIDTH = 8;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_128X8_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_128X8_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -175,6 +187,34 @@ ics55_ecos_sram_128x8_m8 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_128X8_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// One exact 128x8 tile; identical active-low polarity, direct connection.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
gf180mcu_fd_ip_sram__sram128x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (CEN ),
.GWEN (GWEN ),
.WEN (WEN ),
.A (A ),
.D (D ),
`ifndef SYNTHESIS
.Q (Q ),
.VDD (s_vdd),
.VSS (s_vss)
`else
.Q (Q )
`endif
);
`else
// //********************************************************
// //* FPGA memory *
@@ -199,6 +239,10 @@ aq_f_spsram_128x8 x_aq_f_spsram_128x8 (
`undef _AQ_SPSRAM_128X8_ICS55_
`endif
`ifdef _AQ_SPSRAM_128X8_GF180_
`undef _AQ_SPSRAM_128X8_GF180_
`endif
// &Instance("aq_umc_spsram_128x8"); @49
// &Instance("aq_tsmc_spsram_128x8"); @55
// &ModuleEnd; @58
rtl/mini/ip_overrides/aq_spsram_2048x32.v
+66 -3
View File
@@ -12,9 +12,13 @@
// registered on read transactions (manual section 3.1.5 stacking). With
// PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the exact-geometry
// ics55_ecos_sram_2048x32_m8 macro replaces it directly (identical
// active-low polarity, no stacking or padding). Every other configuration
// keeps the upstream behavioral aq_f_spsram_2048x32 instance byte-identical.
// Keep in sync when the lock revision changes.
// active-low polarity, no stacking or padding). With PDK_GF180+
// HAVE_SRAM_MACRO and without PDK_BEHAV, GF180
// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (four deep selected by
// A[10:9] with a registered read mux, times four wide; the repo-owned
// functional models live in rtl/tech/gf180_sram_sim_cells.sv). Every other
// configuration keeps the upstream behavioral aq_f_spsram_2048x32 instance
// byte-identical. Keep in sync when the lock revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -91,6 +95,14 @@ parameter WE_WIDTH = 32;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_2048X32_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_2048X32_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -169,6 +181,53 @@ ics55_ecos_sram_2048x32_m8 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_2048X32_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Sixteen 512x8 tiles: four deep selected by A[10:9] with the bank select
// registered on read transactions, times four wide.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [127:0] s_q;
reg [1:0] s_rd_sel_q;
genvar g_d;
genvar g_w;
always @(posedge CLK) begin
if (!CEN && GWEN) begin
s_rd_sel_q <= A[10:9];
end
end
assign Q = s_q[s_rd_sel_q*32 +: 32];
generate
for (g_d = 0; g_d < 4; g_d = g_d + 1) begin : gen_depth
for (g_w = 0; g_w < 4; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (~(~CEN & (A[10:9] == g_d))),
.GWEN (GWEN ),
.WEN (WEN[g_w*8 +: 8] ),
.A (A[8:0] ),
.D (D[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_d*32 + g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_d*32 + g_w*8 +: 8] )
`endif
);
end
end
endgenerate
`else
//********************************************************
//* FPGA memory *
@@ -193,6 +252,10 @@ aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 (
`undef _AQ_SPSRAM_2048X32_ICS55_
`endif
`ifdef _AQ_SPSRAM_2048X32_GF180_
`undef _AQ_SPSRAM_2048X32_GF180_
`endif
// &Instance("aq_tsmc_spsram_2048x32"); @49
// &Instance("aq_umc_spsram_2048x32"); @61
rtl/mini/ip_overrides/aq_spsram_256x59.v
+61 -3
View File
@@ -14,9 +14,12 @@
// (manual section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and
// without PDK_BEHAV, the exact-geometry ics55_ecos_sram_256x59_m4 macro
// replaces it directly (identical active-low polarity, no stacking or
// padding). Every other configuration keeps the upstream behavioral
// aq_f_spsram_256x59 instance byte-identical. Keep in sync when the lock
// revision changes.
// padding). With PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eight
// GF180 gf180mcu_fd_ip_sram__sram256x8m8wm1 tiles width-stack it (the top
// tile's upper 5 bits are tied inactive; the repo-owned functional models
// live in rtl/tech/gf180_sram_sim_cells.sv). Every other configuration
// keeps the upstream behavioral aq_f_spsram_256x59 instance byte-identical.
// Keep in sync when the lock revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -93,6 +96,14 @@ parameter WE_WIDTH = 59;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_256X59_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_256X59_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -157,6 +168,49 @@ ics55_ecos_sram_256x59_m4 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_256X59_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Eight 256x8 tiles width-stack the 59-bit word; the top tile's upper 5
// bits are tied inactive so they are never written.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [63:0] s_din_ext;
wire [63:0] s_wen_ext;
wire [63:0] s_q;
wire [4:0] s_q_unused;
genvar g_w;
assign s_din_ext = {5'b00000, D};
assign s_wen_ext = {5'b11111, WEN};
assign Q = s_q[58:0];
assign s_q_unused = s_q[63:59];
generate
for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram256x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (CEN ),
.GWEN (GWEN ),
.WEN (s_wen_ext[g_w*8 +: 8] ),
.A (A ),
.D (s_din_ext[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_w*8 +: 8] )
`endif
);
end
endgenerate
`else
//********************************************************
//* FPGA memory *
@@ -181,6 +235,10 @@ aq_f_spsram_256x59 x_aq_f_spsram_256x59 (
`undef _AQ_SPSRAM_256X59_ICS55_
`endif
`ifdef _AQ_SPSRAM_256X59_GF180_
`undef _AQ_SPSRAM_256X59_GF180_
`endif
// &Instance("aq_tsmc_spsram_256x59"); @49
// &Instance("aq_umc_spsram_256x59"); @61
rtl/mini/ip_overrides/aq_spsram_64x58.v
+62 -3
View File
@@ -11,9 +11,13 @@
// bits are used and the upper mask bits are tied off so they are never
// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
// exact-geometry ics55_ecos_sram_64x58_m4 macro replaces it directly
// (identical active-low polarity, no stacking or padding). Every other
// configuration keeps the upstream behavioral aq_f_spsram_64x58 instance
// byte-identical. Keep in sync when the lock revision changes.
// (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eight GF180
// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it (the top tile's
// upper 6 bits are tied inactive; the repo-owned functional models live in
// rtl/tech/gf180_sram_sim_cells.sv). Every other configuration keeps the
// upstream behavioral aq_f_spsram_64x58 instance byte-identical. Keep in
// sync when the lock revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -90,6 +94,14 @@ parameter WE_WIDTH = 58;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_64X58_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_64X58_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -137,6 +149,49 @@ ics55_ecos_sram_64x58_m4 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_64X58_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Eight 64x8 tiles width-stack the 58-bit word; the top tile's upper 6
// bits are tied inactive so they are never written.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [63:0] s_din_ext;
wire [63:0] s_wen_ext;
wire [63:0] s_q;
wire [5:0] s_q_unused;
genvar g_w;
assign s_din_ext = {6'b000000, D};
assign s_wen_ext = {6'b111111, WEN};
assign Q = s_q[57:0];
assign s_q_unused = s_q[63:58];
generate
for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (CEN ),
.GWEN (GWEN ),
.WEN (s_wen_ext[g_w*8 +: 8] ),
.A (A ),
.D (s_din_ext[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_w*8 +: 8] )
`endif
);
end
endgenerate
`else
// //********************************************************
// //* FPGA memory *
@@ -161,6 +216,10 @@ aq_f_spsram_64x58 x_aq_f_spsram_64x58 (
`undef _AQ_SPSRAM_64X58_ICS55_
`endif
`ifdef _AQ_SPSRAM_64X58_GF180_
`undef _AQ_SPSRAM_64X58_GF180_
`endif
// &Instance("aq_umc_spsram_64x58"); @49
// &Instance("aq_tsmc_spsram_64x58"); @55
// &ModuleEnd; @58
rtl/mini/ip_overrides/aq_spsram_64x88.v
+55 -3
View File
@@ -12,9 +12,13 @@
// mask bits tied off so they are never written (manual section 3.1.5
// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
// exact-geometry ics55_ecos_sram_64x88_m4 macro replaces it directly
// (identical active-low polarity, no stacking or padding). Every other
// configuration keeps the upstream behavioral aq_f_spsram_64x88 instance
// byte-identical. Keep in sync when the lock revision changes.
// (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eleven GF180
// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it exactly (the
// repo-owned functional models live in rtl/tech/gf180_sram_sim_cells.sv).
// Every other configuration keeps the upstream behavioral
// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock
// revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -91,6 +95,14 @@ parameter WE_WIDTH = 88;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_64X88_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_64X88_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -160,6 +172,42 @@ ics55_ecos_sram_64x88_m4 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_64X88_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Eleven 64x8 tiles width-stack the 88-bit word exactly.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [87:0] s_q;
genvar g_w;
assign Q = s_q;
generate
for (g_w = 0; g_w < 11; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (CEN ),
.GWEN (GWEN ),
.WEN (WEN[g_w*8 +: 8] ),
.A (A ),
.D (D[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_w*8 +: 8] )
`endif
);
end
endgenerate
`else
//********************************************************
//* FPGA memory *
@@ -185,6 +233,10 @@ aq_f_spsram_64x88 x_aq_f_spsram_64x88 (
`undef _AQ_SPSRAM_64X88_ICS55_
`endif
`ifdef _AQ_SPSRAM_64X88_GF180_
`undef _AQ_SPSRAM_64X88_GF180_
`endif
// &Instance("aq_tsmc_spsram_64x88"); @50
// &Instance("aq_umc_spsram_64x88"); @62
rtl/mini/ip_overrides/aq_spsram_64x98.v
+62 -3
View File
@@ -12,9 +12,13 @@
// mask bits tied off so they are never written (manual section 3.1.5
// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the
// exact-geometry ics55_ecos_sram_64x98_m4 macro replaces it directly
// (identical active-low polarity, no stacking or padding). Every other
// configuration keeps the upstream behavioral aq_f_spsram_64x98 instance
// byte-identical. Keep in sync when the lock revision changes.
// (identical active-low polarity, no stacking or padding). With
// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, thirteen GF180
// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it (the top tile's
// upper 6 bits are tied inactive; the repo-owned functional models live in
// rtl/tech/gf180_sram_sim_cells.sv). Every other configuration keeps the
// upstream behavioral aq_f_spsram_64x98 instance byte-identical. Keep in
// sync when the lock revision changes.
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
@@ -91,6 +95,14 @@ parameter WE_WIDTH = 98;
`endif
`endif
`ifdef PDK_GF180
`ifdef HAVE_SRAM_MACRO
`ifndef PDK_BEHAV
`define _AQ_SPSRAM_64X98_GF180_
`endif
`endif
`endif
`ifdef _AQ_SPSRAM_64X98_IHP130_
//********************************************************
//* IHP130 SRAM macro *
@@ -160,6 +172,49 @@ ics55_ecos_sram_64x98_m4 u_mem (
.WEB (WEN ),
.Q (Q )
);
`elsif _AQ_SPSRAM_64X98_GF180_
//********************************************************
//* GF180 SRAM macro *
//********************************************************
// Thirteen 64x8 tiles width-stack the 98-bit word; the top tile's upper 6
// bits are tied inactive so they are never written.
`ifndef SYNTHESIS
wire s_vdd;
wire s_vss;
assign s_vdd = 1'b1;
assign s_vss = 1'b0;
`endif
wire [103:0] s_din_ext;
wire [103:0] s_wen_ext;
wire [103:0] s_q;
wire [5:0] s_q_unused;
genvar g_w;
assign s_din_ext = {6'b000000, D};
assign s_wen_ext = {6'b111111, WEN};
assign Q = s_q[97:0];
assign s_q_unused = s_q[103:98];
generate
for (g_w = 0; g_w < 13; g_w = g_w + 1) begin : gen_width
gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem (
.CLK (CLK ),
.CEN (CEN ),
.GWEN (GWEN ),
.WEN (s_wen_ext[g_w*8 +: 8] ),
.A (A ),
.D (s_din_ext[g_w*8 +: 8] ),
`ifndef SYNTHESIS
.Q (s_q[g_w*8 +: 8] ),
.VDD (s_vdd ),
.VSS (s_vss )
`else
.Q (s_q[g_w*8 +: 8] )
`endif
);
end
endgenerate
`else
//********************************************************
//* FPGA memory *
@@ -185,6 +240,10 @@ aq_f_spsram_64x98 x_aq_f_spsram_64x98 (
`undef _AQ_SPSRAM_64X98_ICS55_
`endif
`ifdef _AQ_SPSRAM_64X98_GF180_
`undef _AQ_SPSRAM_64X98_GF180_
`endif
// &Instance("aq_tsmc_spsram_64x98"); @50
// &Instance("aq_umc_spsram_64x98"); @62