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feat: add xtal pad into the tech module

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maksyuki committed 2025-01-31 01:14:08 +08:00
1 parent 4a37a12b05
commit bd423766ab
3 files changed
+36 -26
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tech/tc_clk.v
+1 -1
View File
@@ -81,4 +81,4 @@ module ihp_clk_gating #(
assign clk_o = clk_i;
// end
endmodule
endmodule
tech/tc_io.v
+11 -1
View File
@@ -1,3 +1,13 @@
module ihp_io_xtl_pad (
input xi_pad,
output xo_pad,
input en,
output clk
);
assign clk = en ? xi_pad : 1'b0;
endmodule
module ihp_io_tri_pad (
inout pad,
input c2p,
@@ -13,4 +23,4 @@ module ihp_io_tri_pad (
.p2c (p2c)
);
endmodule
endmodule
tech/tc_sram.v
+24 -24
View File
@@ -53,27 +53,27 @@ module tc_sram_1024x32 (
endmodule
// 4KB
module SPRAM1024X16 (
input clk_i,
input cs_i,
input [ 9:0] addr_i,
input [15:0] data_i,
input [ 3:0] mask_i,
input wren_i,
output reg [15:0] data_o
);
reg [15:0] mem[0:1023];
always @(posedge clk_i) begin
if (cs_i) begin
if (!wren_i) begin
data_o <= mem[addr_i];
end else begin
if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
data_o <= 32'bx;
end
end
end
endmodule
// module SPRAM1024X16 (
// input clk_i,
// input cs_i,
// input [ 9:0] addr_i,
// input [15:0] data_i,
// input [ 3:0] mask_i,
// input wren_i,
// output reg [15:0] data_o
// );
// reg [15:0] mem[0:1023];
// always @(posedge clk_i) begin
// if (cs_i) begin
// if (!wren_i) begin
// data_o <= mem[addr_i];
// end else begin
// if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
// if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
// if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
// if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
// data_o <= 32'bx;
// end
// end
// end
// endmodule