mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
dd3ee032b2
Implement the memory replacement required by chapter 3 of the OpenC906 integration manual for the Mini HP core. The eight aq_spsram_* single-port SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag) gain reviewed overrides in rtl/mini/ip_overrides/, registered in scripts/generate_openc906.py with sha256 pins on the vendored files at the locked revision b0c06eb1. Each override keeps the upstream behavioral aq_f_spsram_* instance byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual section 3.1.5 (depth stacks with a read-registered bank select, width stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off, matching the tc_sram.sv convention. Committed CI profiles keep PDK_BEHAV=YES, so their simulation results are unchanged. The Makefile also lists the new overrides as prerequisites of the generated-filelist stamp so editing one forces regeneration. Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus) and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on the macro path.
170 lines
4.5 KiB
Verilog
170 lines
4.5 KiB
Verilog
// retroSoC controlled override of the vendored OpenC906 aq_spsram_2048x32.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_2048x32.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with
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// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 2048x32 ICache data
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// RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a depth
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// stack: A[10] selects the bank and the read-data mux uses the bank select
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// registered on read transactions (manual section 3.1.5 stacking). Every
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// other configuration keeps the upstream behavioral aq_f_spsram_2048x32
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// instance byte-identical. Keep in sync when the lock revision changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module aq_spsram_2048x32(
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A,
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CEN,
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CLK,
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D,
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GWEN,
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Q,
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WEN
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);
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// &Ports; @23
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input [10:0] A;
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input CEN;
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input CLK;
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input [31:0] D;
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input GWEN;
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input [31:0] WEN;
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output [31:0] Q;
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// &Regs; @24
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// &Wires; @25
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wire [10:0] A;
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wire CEN;
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wire CLK;
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wire [31:0] D;
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wire GWEN;
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wire [31:0] Q;
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wire [31:0] WEN;
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//**********************************************************
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// Parameter Definition
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//**********************************************************
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parameter ADDR_WIDTH = 11;
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parameter DATA_WIDTH = 32;
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parameter WE_WIDTH = 32;
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// &Force("bus","Q",DATA_WIDTH-1,0); @34
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// &Force("bus","WEN",WE_WIDTH-1,0); @35
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// &Force("bus","A",ADDR_WIDTH-1,0); @36
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// &Force("bus","D",DATA_WIDTH-1,0); @37
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`ifdef PDK_IHP130
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`ifdef HAVE_SRAM_MACRO
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`ifndef PDK_BEHAV
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`define _AQ_SPSRAM_2048X32_IHP130_
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`endif
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`endif
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`endif
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`ifdef _AQ_SPSRAM_2048X32_IHP130_
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//********************************************************
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//* IHP130 SRAM macro *
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//********************************************************
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// Two 1024x32 macros are depth-stacked into 2048x32: A[10] chip-selects the
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// bank, and the read-data mux uses the bank select registered on reads.
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wire s_en_lo;
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wire s_en_hi;
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wire [31:0] s_q_lo;
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wire [31:0] s_q_hi;
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reg s_rd_sel_q;
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assign s_en_lo = ~CEN & ~A[10];
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assign s_en_hi = ~CEN & A[10];
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always @(posedge CLK) begin
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if (!CEN && GWEN) begin
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s_rd_sel_q <= A[10];
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end
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end
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assign Q = s_rd_sel_q ? s_q_hi : s_q_lo;
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RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_lo (
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.A_CLK (CLK ),
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.A_ADDR (A[9:0] ),
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.A_BM (~WEN ),
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.A_MEN (s_en_lo ),
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.A_WEN (~GWEN ),
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.A_REN (GWEN ),
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.A_DIN (D ),
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.A_DOUT (s_q_lo ),
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.A_DLY (1'b1 ),
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.A_BIST_CLK (1'b0 ),
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.A_BIST_EN (1'b0 ),
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.A_BIST_MEN (1'b0 ),
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.A_BIST_WEN (1'b0 ),
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.A_BIST_REN (1'b0 ),
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.A_BIST_ADDR(10'b0 ),
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.A_BIST_DIN (32'b0 ),
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.A_BIST_BM (32'b0 )
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);
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RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi (
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.A_CLK (CLK ),
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.A_ADDR (A[9:0] ),
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.A_BM (~WEN ),
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.A_MEN (s_en_hi ),
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.A_WEN (~GWEN ),
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.A_REN (GWEN ),
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.A_DIN (D ),
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.A_DOUT (s_q_hi ),
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.A_DLY (1'b1 ),
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.A_BIST_CLK (1'b0 ),
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.A_BIST_EN (1'b0 ),
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.A_BIST_MEN (1'b0 ),
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.A_BIST_WEN (1'b0 ),
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.A_BIST_REN (1'b0 ),
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.A_BIST_ADDR(10'b0 ),
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.A_BIST_DIN (32'b0 ),
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.A_BIST_BM (32'b0 )
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);
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`else
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//********************************************************
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//* FPGA memory *
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//********************************************************
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// &Instance("aq_f_spsram_2048x32"); @43
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aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 (
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.A (A ),
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.CEN (CEN ),
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.CLK (CLK ),
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.D (D ),
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.GWEN (GWEN),
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.Q (Q ),
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.WEN (WEN )
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);
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`endif
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`ifdef _AQ_SPSRAM_2048X32_IHP130_
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`undef _AQ_SPSRAM_2048X32_IHP130_
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`endif
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// &Instance("aq_tsmc_spsram_2048x32"); @49
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// &Instance("aq_umc_spsram_2048x32"); @61
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// &ModuleEnd; @65
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endmodule
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