- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
- Updated formal.mk to include PSRAM in formal verification targets and source files.
- Modified software.mk to include psram_math.c for HAL.
- Enhanced pin_map.json to map GPIO pins for PSRAM control signals.
- Refactored ip_ribp_wrapper.sv to integrate PSRAM interface and remove unused ribp interfaces.
- Updated rtl_style_audit.json to include PSRAM related files.
- Added PSRAM testbench (psram_tb.sv) for integration testing.
- Created test_psram.py to validate PSRAM controller functionality and register offsets.
- Adjusted memory map tests to reflect new PSRAM address space and size.
- Enhanced the RTL style checker script to include new diagnostic rules for function declarations, primary design units, and synthesis exclusions.
- Added functions to handle audit issues, ensuring that the audit records match the current inventory of RTL files.
- Updated test cases to reflect changes in RTL file names and paths, ensuring consistency with the new naming conventions.
- Introduced additional tests for style violations, including mismatched primary design units and synthesizable initial blocks.
- Adjusted file paths in various test files to align with the new RTL structure and naming conventions.
- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types.
- Introduced address generation logic for read and write operations based on burst parameters.
- Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol.
- Modified the SDRAM controller and testbench to accommodate the new burst handling features.
- Enhanced test cases to verify the correct behavior of burst transactions and address patterns.
- Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.
- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure.
- Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency.
- Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure.
- Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated and to reflect changes in bus naming conventions.
- Enhanced to include AXI4-Stream interface checks and validate stream data transfers.
- Modified to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
- Deleted the UART interface and related components from the RTL design, including the UART TX/RX signals and instances.
- Removed the timer interface and its associated files from the project, including the timer definitions and references in the integration files.
- Updated the APB target configurations to reflect the removal of the UART and timer components, ensuring the IRQ and memory map configurations are consistent.
- Adjusted the formal verification properties and testbenches to exclude references to the removed components.
- Cleaned up the integration documentation to accurately describe the current state of the system without the UART and timer interfaces.
- Introduced signal in sysctrl interface and module to handle RTC wake events.
- Added RTC wake status register in memory map and updated related tests.
- Integrated RTC wake handling in the APB wrapper and core wrapper.
- Enhanced clock and reset domain configurations to include RTC signals.
- Updated software build configurations to include RTC source files and headers.
- Modified formal verification and testbench files to accommodate RTC wake functionality.
- Ensured proper synchronization and status recording for RTC wake events in the sysctrl module.
- Updated Makefile to include a check for the RNG metadata script and added a dependency for it.
- Modified memory_map.json to change the user access level of APB_RNG to 'none'.
- Updated clusterip filelist to include new RNG source files.
- Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ.
- Updated soc_topology.json to reflect the new RNG interrupt configuration.
- Added RNG source files to software.mk for compilation.
- Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface.
- Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined.
- Modified test_script_tools.py to ensure dry runs do not write filelists.
- Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.
- Updated to include for testing.
- Modified to include GPIO header and added tests for GPIO functionality.
- Created a new testbench for GPIO V2, covering register and pad-control contracts.
- Removed obsolete and its associated test.
- Updated to include GPIO admin base routing.
- Added a new Python test for GPIO V2 register and pad-control contract.
- Removed as its functionality is now covered in .
- Updated memory map tests to ensure GPIO admin base is correctly referenced.
- Adjusted formal filelist generation to reflect changes in GPIO handling.
- Enhanced SOC topology tests to include GPIO interrupt handling.
- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.
- Introduced test status signals (test_done_o, test_pass_o, test_code_o) in sysctrl interface and module.
- Updated memory map to include TEST_STATUS offset.
- Enhanced retrosoc_tb to monitor test completion and report results.
- Modified Emulator to handle test status and return appropriate exit codes.
- Updated formal verification to include assertions for test status.
- Added CoreMark log parsing script and integrated it into the regression tests.
- Implemented tests for test status handling in sysctrl_fault_tb.
- Adjusted simulation success and failure markers in various scripts and tests.
- Ensured compatibility with existing performance logging and regression testing frameworks.
- Renamed and to and respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench to validate RIB to RAM interactions.
- Created for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
- Introduced to define formal properties for the sysctrl module.
- Updated to include new formal properties and source files.
- Renamed to in the bus module and created a new file.
- Implemented a testbench for in .
- Removed the obsolete test file.
- Updated test scripts to reference the new instead of the old RAM module.
- Adjusted various test files to ensure compatibility with the new structure and naming conventions.
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Updated NMI interface references from to in multiple files for consistency.
- Added a new script to convert UART performance records into structured JSON format.
- Enhanced the README documentation to include details about the new performance log parser.
- Implemented tests for the new performance log parser to ensure correct functionality.
- Added new test cases for DMA error handling and SDRAM data integrity to improve coverage.
- Updated existing test cases to accommodate changes in the NMI interface and added performance metrics.
- Refactored bus fault testbench to include fault code checks and improved error handling.
- Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.
- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc.
- Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing.
- Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization.
- Enhanced memory map tests to verify PLL configuration and status offsets.
- Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
- Introduced for handling QSPI flash memory operations, including command and address handling.
- Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C.
- Created for the flash memory implementation, supporting initialization, reading, and memory copying.
- Updated to integrate the new QSPI Flash module and connect it with the existing system.
- Refactored file paths in various filelists and scripts to accommodate the new directory structure under .
- Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure.
- Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
- Updated core_wrapper and mgmt_core_wrapper to use new SOC reset and IRQ addresses.
- Removed obsolete mmap_define.svh file and integrated memory map generation into the build process.
- Enhanced ip_nmi_wrapper to handle fault signals and updated NMI interface assignments.
- Added bus fault and sysctrl fault testbenches to validate fault handling mechanisms.
- Improved memory map generation script and added tests for memory map validation and fault responder behavior.
maksyuki