- Introduced to validate AXI4 interface for 64-bit on-chip SRAM.
- Added to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated to include resource controller interface.
- Enhanced to cover additional IRQ scenarios.
- Added new tests in for AXI4 target guard timeout and isolation.
- Updated to reflect changes in the high-performance profile.
- Modified to verify on-chip SRAM bank configurations.
- Added for directed verification of resource controller.
- Updated to check SDRAM mapped window coverage.
- Enhanced to ensure correct IRQ mappings and APB target generation.
- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
- Introduced to handle the preparation of the SKY130 OpenRAM SRAM views.
- Updated to download and prepare the SRAM archive during PDK setup.
- Enhanced OpenSTA and Yosys configurations to accommodate SRAM macro integration.
- Added Verilog simulation models for GF180 and SKY130 SRAM macros.
- Implemented tests for SRAM setup and validation, ensuring correct integration and functionality.
- Updated various Makefiles and scripts to support SRAM size and macro configurations.
- Updated filelist to include new XPI source files.
- Modified IRQ compatibility mapping for XPI in the SOC topology generator.
- Adjusted JSON topology configuration to reflect new IRQ signal naming.
- Changed software.mk to reference the new XPI HAL source file.
- Enhanced APB4 peripheral module to include XPI IRQ signal.
- Updated RTL style audit to include new XPI files.
- Documented new XPI programming script in README.
- Added a new script for programming XPI flash through OpenOCD.
- Enhanced XPI IO testbench to validate new LUT engine and isolation behavior.
- Created unit tests for the new XPI programming tool and its functionalities.
- Introduced signal in sysctrl interface and module to handle RTC wake events.
- Added RTC wake status register in memory map and updated related tests.
- Integrated RTC wake handling in the APB wrapper and core wrapper.
- Enhanced clock and reset domain configurations to include RTC signals.
- Updated software build configurations to include RTC source files and headers.
- Modified formal verification and testbench files to accommodate RTC wake functionality.
- Ensured proper synchronization and status recording for RTC wake events in the sysctrl module.
- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.
- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files.
- Updated the Emulator class to remove JTAG-related debug signals and configurations.
- Adjusted the pin map and JSON configurations to exclude debug-related entries.
- Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core.
- Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions.
- Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.
- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated and modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
- Updated NMI interface references from to in multiple files for consistency.
- Added a new script to convert UART performance records into structured JSON format.
- Enhanced the README documentation to include details about the new performance log parser.
- Implemented tests for the new performance log parser to ensure correct functionality.
- Added new test cases for DMA error handling and SDRAM data integrity to improve coverage.
- Updated existing test cases to accommodate changes in the NMI interface and added performance metrics.
- Refactored bus fault testbench to include fault code checks and improved error handling.
- Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.
- Introduced Verilator and Yosys warning configurations for ICS55.
- Updated RTL filelists to include functional models for ICS55.
- Modified memory modules to use wire instead of logic for clock and reset signals.
- Enhanced Makefile and Iverilog configurations to support ICS55.
- Implemented new simulation cells for ICS55 in the tech library.
- Updated regression scripts and tests to include ICS55 support.
- Added functionality to prepare ICS55 liberty and simulation models.
- Enhanced testbench to validate ICS55 specific components and behaviors.
- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
- Introduced new JSON files for warnings generated by Icarus Verilog, Verilator, and Yosys for both GF180 and SKY130 PDKs.
- Updated the build requirements to include necessary packages for handling JSON data.
- Modified RTL filelists to use generated files for GF180 and SKY130 standard-cell models.
- Enhanced the Iverilog makefile to generate filelists dynamically based on the selected PDK.
- Implemented a Python script to generate Iverilog filelists, accommodating both GF180 and SKY130 technologies.
- Added behavioral definitions for GF180 UDPs and a tri-state buffer for netlist simulations.
- Updated Yosys synthesis scripts to handle new PDKs and ensure proper tie cell mapping.
- Extended regression scripts to support PDK-specific commands for GF180 and SKY130.
- Added tests to verify that PDK-specific regression commands cover firmware, RTL, and netlist simulations.
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if.
- Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface.
- Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs.
- Removed legacy GPIO handling from retrosoc and retrosoc_asic modules.
- Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files.
- Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py.
- Created new makefiles for IP MDD configurations to support the updated GPIO structure.
- Updated regression tests to include new configurations and ensure compatibility with the changes.
- Adjusted variable alignment in Makefiles for better readability.
- Ensured consistent formatting across various Makefiles and scripts.
- Added a new .bake.toml file to define project formatting policies for mbake.
- Updated paths and variable definitions in multiple configuration files to enhance clarity.
- Removed unnecessary comments and whitespace for cleaner code.
- Updated the default output path in to .
- Introduced a new file to define excluded prefixes, compatibility files, and forbidden calls for embedded C sources.
- Modified to improve compiler flags and source file organization.
- Added scripts for checking C warnings and embedded C compliance, ensuring self-owned sources are validated against the policy.
- Implemented regression tests to capture and report self-owned C compiler warnings during builds.
- Created a new test suite for runtime tests of SDK utilities, ensuring deterministic behavior.
- Enhanced existing test scripts to include checks for C warnings and compliance with the embedded C policy.
- Updated to utilize a new dependency locking mechanism and improved repository management.
- Introduced for running regression tests with configurable command sets for different profiles.
- Added to execute commands with structured logging and result reporting.
- Enhanced to support fetching specific revisions from git repositories.
- Modified to use the new dependency source structure.
- Updated OpenSTA makefile and TCL script to include metrics reporting.
- Improved synthesis scripts to utilize the new flow execution model.
- Added tests for dependency locking, flow execution, and warning analysis.
- Ensured that all scripts and tools are consistent with the new structure and functionality.
maksyuki