- Updated Makefile to include a check for the RNG metadata script and added a dependency for it.
- Modified memory_map.json to change the user access level of APB_RNG to 'none'.
- Updated clusterip filelist to include new RNG source files.
- Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ.
- Updated soc_topology.json to reflect the new RNG interrupt configuration.
- Added RNG source files to software.mk for compilation.
- Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface.
- Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined.
- Modified test_script_tools.py to ensure dry runs do not write filelists.
- Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.
- Introduced scripts and makefile targets for generating architecture information metadata.
- Updated the filelist generation to include archinfo metadata files.
- Modified software.mk to include archinfo source files and headers.
- Enhanced the ip_apb_wrapper and user_ip_wrapper to integrate archinfo components.
- Updated tests to ensure stability and correct path expansions for generated files.
- Removed unnecessary files from the clusterip filelist.
- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files.
- Updated the Emulator class to remove JTAG-related debug signals and configurations.
- Adjusted the pin map and JSON configurations to exclude debug-related entries.
- Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core.
- Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions.
- Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.
- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated and modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
- Added .dockerignore to exclude unnecessary files from Docker context.
- Updated Makefile to include a new setup-regression target for installing dependencies for all PR PDK profiles.
- Enhanced README with installation instructions for Docker and Nix environments.
- Created Dockerfile for a lock-pinned Ubuntu 22.04 development image.
- Added entrypoint script for Docker container to set up the environment.
- Introduced flake.lock and flake.nix for Nix package management.
- Updated dependency_lock.py to validate Nix inputs and container images in the lock file.
- Implemented development_environment.py for managing the development environment setup.
- Enhanced package.py to include container components in the SBOM.
- Added tests to ensure the development environment contract is lock-pinned and validate container and Nix environment files.
- Renamed and to and respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench to validate RIB to RAM interactions.
- Created for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Introduced Verilator and Yosys warning configurations for ICS55.
- Updated RTL filelists to include functional models for ICS55.
- Modified memory modules to use wire instead of logic for clock and reset signals.
- Enhanced Makefile and Iverilog configurations to support ICS55.
- Implemented new simulation cells for ICS55 in the tech library.
- Updated regression scripts and tests to include ICS55 support.
- Added functionality to prepare ICS55 liberty and simulation models.
- Enhanced testbench to validate ICS55 specific components and behaviors.
- Added formal verification support for bus and nmi2apb protocols using SymbiYosys and Bitwuzla.
- Introduced new formal design and properties files for both protocols.
- Updated the build system to include formal verification steps in the Makefile.
- Enhanced the doctor script to check for formal tool availability.
- Added scripts for generating formal file lists and SymbiYosys configurations.
- Implemented a wrapper for Bitwuzla to adapt Yosys legacy arguments.
- Updated documentation to reflect new formal verification capabilities.
- Added tests to ensure correctness of formal file generation and result summarization.
- Updated gen_iverilog_filelist.py to exclude sequential models from the file list for GF180 PDK.
- Introduced black box definitions for GF180 and SKY130 IO cells in their respective .sv files.
- Added simulation models for GF180 IO cells and sequential cells in gf180_seq_sim_cells.v.
- Modified tc_clk.sv to utilize specific clock cells for GF180 and SKY130 PDKs.
- Implemented bi-directional and tri-state pad modules for GF180 and SKY130 PDKs in tc_io.sv.
- Enhanced dependency lock validation to include submodule checks in dependency_lock.py.
- Updated setup_helpers.py to support selective submodule initialization.
- Created a comprehensive testbench for PDK cells in tc_pdk_cells_tb.sv.
- Added tests for dependency helper functions and tech cell configurations to ensure proper error handling.
- Introduced new JSON files for warnings generated by Icarus Verilog, Verilator, and Yosys for both GF180 and SKY130 PDKs.
- Updated the build requirements to include necessary packages for handling JSON data.
- Modified RTL filelists to use generated files for GF180 and SKY130 standard-cell models.
- Enhanced the Iverilog makefile to generate filelists dynamically based on the selected PDK.
- Implemented a Python script to generate Iverilog filelists, accommodating both GF180 and SKY130 technologies.
- Added behavioral definitions for GF180 UDPs and a tri-state buffer for netlist simulations.
- Updated Yosys synthesis scripts to handle new PDKs and ensure proper tie cell mapping.
- Extended regression scripts to support PDK-specific commands for GF180 and SKY130.
- Added tests to verify that PDK-specific regression commands cover firmware, RTL, and netlist simulations.
- Updated to validate C, Makefile, and RTL formatting in addition to existing checks for Python, YAML, and GitHub Actions.
- Added new dependencies to for improved formatting and documentation tools.
- Introduced a new script to format or verify tracked self-owned Makefile and RTL sources.
- Improved RTL code formatting across multiple files by ensuring consistent spacing and line endings.
- Refactored various RTL modules to enhance readability and maintainability.
- Added unit tests for the new formatting functionality to ensure correct behavior.
- Introduced for handling QSPI flash memory operations, including command and address handling.
- Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C.
- Created for the flash memory implementation, supporting initialization, reading, and memory copying.
- Updated to integrate the new QSPI Flash module and connect it with the existing system.
- Refactored file paths in various filelists and scripts to accommodate the new directory structure under .
- Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure.
- Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
- Updated to utilize a new dependency locking mechanism and improved repository management.
- Introduced for running regression tests with configurable command sets for different profiles.
- Added to execute commands with structured logging and result reporting.
- Enhanced to support fetching specific revisions from git repositories.
- Modified to use the new dependency source structure.
- Updated OpenSTA makefile and TCL script to include metrics reporting.
- Improved synthesis scripts to utilize the new flow execution model.
- Added tests for dependency locking, flow execution, and warning analysis.
- Ensured that all scripts and tools are consistent with the new structure and functionality.
maksyuki