Commit Graph
829 Commits
Author SHA1 Message Date
maksyuki bd82e77432 feat: use extra verilator artifact to replace comp process in aciton file 2026-03-02 15:01:07 +08:00
maksyuki 6157467915 fix: fix the position of yosys version info 2026-03-02 09:41:56 +08:00
maksyuki e9ed686220 chore: add extra debug info for yosys 2026-03-02 09:39:47 +08:00
maksyuki 6d4a715369 feat: add debug info for yosys download 2026-03-02 09:37:54 +08:00
maksyuki 04474ca084 feat: add artifact config page for yosys 2026-03-02 09:31:42 +08:00
maksyuki 987efcf4f2 chore: use default path for yosys plugin loading 2026-03-01 16:06:15 +08:00
maksyuki ac6971e972 fix: add missing gpio define inc 2026-03-01 16:05:17 +08:00
maksyuki 90abeaaa51 chore: add install yosys tool in the action file 2026-02-28 12:57:28 +08:00
maksyuki 5ea4524276 feat: rm tiny design file 2026-02-07 16:25:21 +08:00
maksyuki 6dbc560416 feat: add init sdio components 2026-02-07 12:38:37 +08:00
maksyuki e1d4b9c319 feat: add init simple gpu module 2026-02-07 12:35:53 +08:00
maksyuki 1970129162 feat: update the test of i2s module 2026-01-31 13:31:53 +08:00
maksyuki 941cbad7c1 feat: add reg and clkgen module of i2s ip 2026-01-31 10:05:53 +08:00
maksyuki 2322acbe9a feat: add multi bit width and sample ratio support 2026-01-30 23:38:35 +08:00
maksyuki 8222c450d7 feat: change aud clk from 12.288 to 18.432M in tb 2026-01-30 18:05:21 +08:00
maksyuki 19f97b5176 style: format some codes and comments in i2s module 2026-01-30 12:36:40 +08:00
maksyuki 68329735e3 feat: add clk div func and reg for the sdram ip 2026-01-29 17:26:54 +08:00
maksyuki 01408139c8 feat: split sdram main func into core module 2026-01-29 13:01:57 +08:00
maksyuki f8759681fa fix: fix the wrong pix cnt reg naming 2026-01-29 12:43:25 +08:00
maksyuki d239278431 feat: add timing param for dvp camera model 2026-01-29 12:17:26 +08:00
maksyuki 51dea870e7 feat: add init version of dvp camera sim model 2026-01-28 17:18:03 +08:00
maksyuki 481d6377d5 chore: rm unused tb port from qspi if 2026-01-27 16:40:14 +08:00
maksyuki e4a8a1ffa1 feat: add init dvp ip design 2026-01-27 16:38:25 +08:00
maksyuki a965becfe8 fix: fix the wrong sdram addr range 2026-01-27 11:17:50 +08:00
maksyuki fa9cba0ae1 fix: fix the static tRFC value in auto refresh phase 2026-01-24 12:48:48 +08:00
maksyuki bd6690455a feat: change the pos of the reg define 2026-01-24 11:27:14 +08:00
maksyuki 03988ffbc0 feat: integrate sdram module into SoC env 2026-01-24 11:03:29 +08:00
maksyuki af83733a91 chore: add 3rd party ip setup script 2026-01-24 11:00:42 +08:00
maksyuki 3896bbaea4 feat: remove high 2 css select signsl of psram module 2026-01-23 10:41:36 +08:00
maksyuki 8ef5799f55 feat: add init new version impl of qspi module 2026-01-21 11:42:15 +08:00
maksyuki cb290f4f5f feat: add QSPI Flash simu model 2026-01-18 13:15:47 +08:00
maksyuki f7debcc7a7 chore: remove unused spifs include path 2026-01-15 00:02:50 +08:00
maksyuki c1ab6fa6c2 feat: remove unused spi flash IP, model and instance 2026-01-13 21:17:32 +08:00
maksyuki 4ded6c3e88 feat: change default clock freq from '48MHz' to '72MHz' 2026-01-12 16:33:04 +08:00
maksyuki 118e3c4ff4 feat: rm unused N25 sim verilog module 2026-01-12 16:31:52 +08:00
maksyuki b7fee8f25b fix: fix the wrong clint base addr and add init sdram addr 2026-01-11 13:18:29 +08:00
maksyuki b5a9c9499e fix: fix the mismatch bit width for psram module 2026-01-11 13:17:52 +08:00
maksyuki 11c75c7a79 chore: change the ip name for nmi uart module 2026-01-10 23:51:50 +08:00
maksyuki 539b0b2653 style: change style name for nmi timer 2026-01-10 23:45:45 +08:00
maksyuki bf3fbad719 feat: add full func for gpio and remove unused i2c1 and qspi1 sdk 2026-01-10 23:32:23 +08:00
maksyuki 4fc70ee476 feat: remove unused qspi1 and i2c1 from app info 2026-01-10 22:38:35 +08:00
maksyuki d4a23a0824 feat: mv the pos of gpio ip into right place 2026-01-10 22:24:06 +08:00
maksyuki 29dd18f88b fix: fix a wrror port connect 2026-01-10 16:49:37 +08:00
maksyuki 038d18ee1f chore: add config file to filter warnings and linting infos 2026-01-10 16:36:34 +08:00
maksyuki 8905c28561 feat: remove 3rd-party baesd ip implement 2026-01-10 13:03:31 +08:00
maksyuki f95c61d1c9 fix: format the code in vsrc home module 2026-01-09 19:54:00 +08:00
maksyuki 10e4c8e173 feat: opt the rcu clk generate function 2026-01-09 19:50:48 +08:00
maksyuki d12881bfaf feat: change default bps from 115200 to 921600 2026-01-09 13:17:38 +08:00
maksyuki 55867b44a1 fix: add ifconf macro to control synth flow 2026-01-09 10:52:12 +08:00
maksyuki b8f284f287 fix: fix 1-wire and cycle/instret add error 2026-01-06 17:14:08 +08:00