- Updated file lists to include new watchdog RTL files in clusterip.
- Replaced async_reqack source in commonip file list with top-level CDC file.
- Modified clock and reset domain configurations to incorporate watchdog reset signals.
- Updated the SoC topology generation script and JSON to reflect changes in watchdog interrupt handling.
- Added watchdog source files to software makefile for compilation.
- Enhanced APB wrapper to connect watchdog reset request signal.
- Updated RCU module to handle watchdog reset requests.
- Modified testbench to validate watchdog reset functionality.
- Updated test cases to reflect changes in interrupt naming conventions for the watchdog.
- Updated the PS2 interface in the APB wrapper to include RX and TX FIFO depths.
- Replaced the kdb_model with ps2_device_model in the testbench for better PS2 handling.
- Added new PS2 source files and headers for keyboard and mouse functionality.
- Refactored GPIO alternate functions to support PS2 clock and data signals.
- Implemented PS2 decoder tests for keyboard and mouse in the runtime tests.
- Updated the software makefile to include new PS2 source files and headers.
- Modified the topology tests to validate PS2 GPIO assignments.
- Updated Makefile to include a check for the RNG metadata script and added a dependency for it.
- Modified memory_map.json to change the user access level of APB_RNG to 'none'.
- Updated clusterip filelist to include new RNG source files.
- Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ.
- Updated soc_topology.json to reflect the new RNG interrupt configuration.
- Added RNG source files to software.mk for compilation.
- Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface.
- Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined.
- Modified test_script_tools.py to ensure dry runs do not write filelists.
- Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.
- Updated to include I2C1 in IRQ bindings.
- Modified to increase IRQ group width and add I2C1 interrupt.
- Enhanced to include I2C formal properties and adjust timeouts.
- Added I2C-related source files to the formal verification flow.
- Updated DMA wrapper in to handle I2C DMA signals.
- Created a new testbench for I2C functionality verification.
- Implemented I2C helper functions in for testing.
- Added I2C tests in to validate controller behavior and recovery.
- Updated existing tests to accommodate changes in DMA and IRQ handling.
- Updated to include for testing.
- Modified to include GPIO header and added tests for GPIO functionality.
- Created a new testbench for GPIO V2, covering register and pad-control contracts.
- Removed obsolete and its associated test.
- Updated to include GPIO admin base routing.
- Added a new Python test for GPIO V2 register and pad-control contract.
- Removed as its functionality is now covered in .
- Updated memory map tests to ensure GPIO admin base is correctly referenced.
- Adjusted formal filelist generation to reflect changes in GPIO handling.
- Enhanced SOC topology tests to include GPIO interrupt handling.
- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.
- Replace onewire interface with ws2812 interface in retrosoc module.
- Include ws2812_math.c in C test sources.
- Add ws2812 header in test_runtime.c and implement ws2812 helper tests.
- Update ribp_topology_tb and soc_irq_topology_tb to handle ws2812 interface.
- Create ws2812_dma_tb and ws2812_tb for testing WS2812 DMA and waveform functionality.
- Enhance test_script_tools.py to include ws2812 in formal filelists.
- Modify test_soc_topology.py to ensure proper IRQ mapping for ws2812.
- Introduce test_ws2812.py for WS2812 register, waveform, and streaming regression tests.
- Changed the interface from ribp to rib in soc_topology.json and related files.
- Updated formal.mk to reflect the new rib2apb naming convention.
- Implemented rib2apb module to handle RIB to APB communication.
- Modified bus.sv to integrate the new rib2apb module and adjust signal assignments accordingly.
- Updated testbench files to use the new rib interface and validate the RIB to APB functionality.
- Created rib2apb_tb for testing the direct RIB to APB bridge.
- Adjusted script tools and test scripts to accommodate the new naming and structure.
- Renamed and to and respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench to validate RIB to RAM interactions.
- Created for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
- Introduced to define formal properties for the sysctrl module.
- Updated to include new formal properties and source files.
- Renamed to in the bus module and created a new file.
- Implemented a testbench for in .
- Removed the obsolete test file.
- Updated test scripts to reference the new instead of the old RAM module.
- Adjusted various test files to ensure compatibility with the new structure and naming conventions.
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Expanded psel_comb and psel_q to 10 bits in nmi2apb_formal.sv and nmi2apb_formal_props.v.
- Added user_ip interface and corresponding formal slave instance in nmi2apb_formal_design.
- Implemented migration of legacy user-extension includes to user_extensions.svh in generate_mpw.py.
- Enhanced configured_filelist function to accept require_files parameter in export_soc_sources.py.
- Updated tests to validate user extension migration and formal design changes.
- Removed CORE and IP variables from common.tcl and synth.tcl scripts.
- Updated yosys.mk to exclude CORE and IP from environment variables.
- Modified bus_fault_tb to enhance NMI interface with management and user NMI signals.
- Added user access denial handling in bus_fault_tb.
- Updated pll_ctrl_tb and sysctrl_fault_tb to reflect changes in NMI interface.
- Adjusted test_gpio_user_mux.py to remove IP_MDD definition.
- Enhanced memory map tests to include user extensions and ensure proper generation.
- Updated test_script_tools.py to reflect changes in core management and user extensions.
- Refined topology tests to ensure user APB target is always added.
- Adjusted tech cell configuration tests to use simplified profile paths.
- Improved user extensions tests for scalar bindings and slot validation.
- Updated soc_topology.json to include new fabric links for core, DMA, native, and APB interfaces.
- Refactored retrosoc.sv to utilize generated fabric links and included necessary SVH files for better modularity.
- Improved check_clock_reset_domains.py to validate hierarchical pins and added support for positive number checks.
- Modified regress.py to include OpenSTA in the regression commands.
- Enhanced README.md in the STA directory to clarify the timing analysis flow and supported PDK profiles.
- Removed outdated gen2.sdc file and replaced it with a dynamic SDC generation approach.
- Updated opensta.mk to generate SDC files dynamically based on the current domain map and pin map.
- Created generate_sdc.py to automate SDC generation from clock/reset domain inventory.
- Added tests for generated core-STA constraints to ensure coverage of current clock domains and validate pin map integrity.
- Introduced new timing metrics and warnings for the sky130 PDK in the quality checks.
- Added APB target definitions in soc_topology.json for various peripherals.
- Introduced user_extensions.json to define user core and IP targets.
- Updated generate_filelist.py to include SVA paths.
- Refactored ip_apb_wrapper.sv to utilize generated APB interfaces and bridges.
- Simplified user_core_top.sv and user_ip_top.sv by including generated bindings.
- Implemented check_clock_reset_domains.py to validate clock/reset domains and CDC crossings.
- Updated regress.py to include SVA support in simulation commands.
- Added tests for clock/reset domain validation and user extensions generation.
- Enhanced test coverage for topology generation and APB target ownership validation.
- Updated the file to improve code readability and maintainability by removing commented-out code and adding generated GPIO alternate-function wiring.
- Modified to streamline simulation command configurations and removed unnecessary variables.
- Introduced a new testbench to validate NMI routing functionality within the SoC topology.
- Added comprehensive tests in to ensure the correctness of generated bindings and validate topology constraints.
- Adjusted to reflect changes in regression command imports and ensure uniform timeout settings for Verilator simulations.
maksyuki