2 Commits

Include renames

Author	SHA1	Message	Date
maksyuki	fc898bc4ab	feat: add PLL controller and related testbench functionality ... - Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.	2026-07-20 22:12:17 +08:00
maksyuki	82e5c605a8	feat: refactor memory map definitions and enhance fault handling in Mini SoC ... - Updated core_wrapper and mgmt_core_wrapper to use new SOC reset and IRQ addresses. - Removed obsolete mmap_define.svh file and integrated memory map generation into the build process. - Enhanced ip_nmi_wrapper to handle fault signals and updated NMI interface assignments. - Added bus fault and sysctrl fault testbenches to validate fault handling mechanisms. - Improved memory map generation script and added tests for memory map validation and fault responder behavior.	2026-07-20 12:01:48 +08:00