mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
97 lines
2.8 KiB
Systemverilog
97 lines
2.8 KiB
Systemverilog
`timescale 1ns / 1ps
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module sysctrl_fault_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic fault_valid_i = 1'b0;
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logic [31:0] fault_addr_i = '0;
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logic [ 3:0] fault_wstrb_i = '0;
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logic fault_reserved_i = 1'b0;
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nmi_if nmi ();
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sysctrl_if sysctrl ();
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pll_ctrl_if pll_ctrl ();
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always #5 clk_i = ~clk_i;
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nmi_sysctrl u_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.nmi (nmi),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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task automatic read_register(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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nmi.addr = address;
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nmi.wdata = '0;
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nmi.wstrb = '0;
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nmi.valid = 1'b1;
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while (!nmi.ready) @(posedge clk_i);
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data = nmi.rdata;
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@(negedge clk_i);
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nmi.valid = 1'b0;
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while (nmi.ready) @(posedge clk_i);
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end
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endtask
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task automatic write_register(input logic [31:0] address, input logic [31:0] data);
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begin
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@(negedge clk_i);
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nmi.addr = address;
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nmi.wdata = data;
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nmi.wstrb = 4'hF;
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nmi.valid = 1'b1;
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while (!nmi.ready) @(posedge clk_i);
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@(negedge clk_i);
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nmi.valid = 1'b0;
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while (nmi.ready) @(posedge clk_i);
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end
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endtask
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logic [31:0] read_data;
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initial begin
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nmi.valid = 1'b0;
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nmi.addr = '0;
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nmi.wdata = '0;
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nmi.wstrb = '0;
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sysctrl.core_sel_i = '0;
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pll_ctrl.req_ready_i = 1'b1;
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pll_ctrl.rsp_active_sel_i = '0;
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pll_ctrl.rsp_active_valid_i = 1'b0;
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pll_ctrl.rsp_safe_clk_i = 1'b1;
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pll_ctrl.rsp_pll_lock_i = 1'b0;
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pll_ctrl.rsp_error_i = '0;
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pll_ctrl.rsp_valid_i = 1'b0;
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pll_ctrl.capable_i = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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fault_valid_i = 1'b1;
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fault_addr_i = 32'h1000_F000;
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fault_wstrb_i = 4'hF;
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fault_reserved_i = 1'b1;
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@(negedge clk_i);
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fault_valid_i = 1'b0;
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read_register(32'h1000_B010, read_data);
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if (read_data !== 32'h0000_000B) $fatal(1, "fault status was not recorded");
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read_register(32'h1000_B014, read_data);
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if (read_data !== 32'h1000_F000) $fatal(1, "fault address was not recorded");
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read_register(32'h1000_B018, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "fault count was not incremented");
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write_register(32'h1000_B010, 32'h0000_0001);
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read_register(32'h1000_B010, read_data);
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if (read_data !== 32'h0000_000A) $fatal(1, "fault W1C did not clear pending");
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$display("sysctrl fault registers test passed");
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$finish;
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end
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endmodule
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