mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
319 lines
9.7 KiB
Systemverilog
319 lines
9.7 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "axi4_define.svh"
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module axi4_word_bridge_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [31:0] memory [0:63];
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logic [31:0] expected;
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integer target_accesses = 0;
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integer error_beats;
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integer cycle_count = 0;
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integer burst_cycles;
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integer single_cycles;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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logic req_valid;
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logic req_ready;
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logic [31:0] req_addr;
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logic [31:0] req_wdata;
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logic [ 3:0] req_wstrb;
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logic [31:0] req_rdata;
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logic req_resp_err;
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always #5 clk_i = ~clk_i;
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always @(posedge clk_i) cycle_count <= cycle_count + 1;
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axi4_word_bridge u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.axi4 (axi4),
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.req_valid_o (req_valid),
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.req_ready_i (req_ready),
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.req_addr_o (req_addr),
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.req_wdata_o (req_wdata),
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.req_wstrb_o (req_wstrb),
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.req_rdata_i (req_rdata),
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.req_resp_err_i(req_resp_err)
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);
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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req_ready <= 1'b0;
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req_rdata <= '0;
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target_accesses <= 0;
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end else begin
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req_ready <= req_valid && !req_ready;
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if (req_valid && !req_ready) begin
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target_accesses <= target_accesses + 1;
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req_rdata <= memory[req_addr[7:2]];
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for (int lane = 0; lane < 4; lane++) begin
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if (req_wstrb[lane]) begin
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memory[req_addr[7:2]][lane*8+:8] <= req_wdata[lane*8+:8];
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end
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end
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end
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end
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end
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assign req_resp_err = 1'b0;
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task automatic init_axi4;
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begin
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axi4.awid = '0;
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axi4.awaddr = '0;
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axi4.awlen = '0;
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axi4.awsize = `AXI4_BURST_SIZE_4BYTES;
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axi4.awburst = `AXI4_BURST_TYPE_INCR;
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axi4.awlock = `AXI4_LOCK_NORM;
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axi4.awcache = `AXI4_CACHE_NO_BUF;
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axi4.awprot = `AXI4_PROT_DATA;
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axi4.awqos = `AXI4_QOS_NORMAL;
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axi4.awregion = `AXI4_REGION_NORMAL;
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axi4.awuser = '0;
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axi4.awvalid = 1'b0;
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axi4.wdata = '0;
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axi4.wstrb = '0;
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axi4.wlast = 1'b0;
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axi4.wuser = '0;
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axi4.wvalid = 1'b0;
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axi4.bready = 1'b0;
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axi4.arid = '0;
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axi4.araddr = '0;
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axi4.arlen = '0;
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axi4.arsize = `AXI4_BURST_SIZE_4BYTES;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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axi4.arlock = `AXI4_LOCK_NORM;
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axi4.arcache = `AXI4_CACHE_NO_BUF;
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axi4.arprot = `AXI4_PROT_DATA;
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axi4.arqos = `AXI4_QOS_NORMAL;
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axi4.arregion = `AXI4_REGION_NORMAL;
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axi4.aruser = '0;
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b0;
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end
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endtask
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task automatic issue_write4(input logic [31:0] address);
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begin
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@(negedge clk_i);
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axi4.awaddr = address;
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axi4.awlen = 8'd3;
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axi4.awvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.awready);
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@(negedge clk_i);
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axi4.awvalid = 1'b0;
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for (int beat = 0; beat < 4; beat++) begin
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axi4.wdata = 32'hA500_0000 + beat;
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axi4.wstrb = 4'hF;
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axi4.wlast = beat == 3;
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axi4.wvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.wready);
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@(negedge clk_i);
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axi4.wvalid = 1'b0;
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end
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repeat (2) @(posedge clk_i);
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axi4.bready = 1'b1;
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do @(posedge clk_i); while (!axi4.bvalid);
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if (axi4.bresp != `AXI4_RESP_OKAY) $fatal(1, "write burst returned an error");
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@(negedge clk_i);
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axi4.bready = 1'b0;
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end
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endtask
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task automatic issue_read4(input logic [31:0] address);
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begin
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = 8'd3;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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for (int beat = 0; beat < 4; beat++) begin
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if (beat == 1) begin
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repeat (3) @(posedge clk_i);
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@(negedge clk_i);
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end
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axi4.rready = 1'b1;
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do @(posedge clk_i); while (!axi4.rvalid);
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expected = 32'hA500_0000 + beat;
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if (axi4.rdata != expected || axi4.rresp != `AXI4_RESP_OKAY ||
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axi4.rlast != (beat == 3)) begin
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$fatal(1, "read beat %0d mismatch: data=%08x expected=%08x resp=%0d last=%0d", beat,
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axi4.rdata, expected, axi4.rresp, axi4.rlast);
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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end
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end
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endtask
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task automatic issue_illegal_read(input logic [31:0] address);
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integer accesses_before;
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begin
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accesses_before = target_accesses;
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = 8'd16;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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error_beats = 0;
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while (error_beats < 17) begin
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@(posedge clk_i);
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if (axi4.rvalid) begin
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if (axi4.rresp != `AXI4_RESP_SLAVE_ERROR || axi4.rlast != (error_beats == 16)) begin
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$fatal(1, "illegal burst response mismatch");
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end
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error_beats = error_beats + 1;
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end
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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if (target_accesses != accesses_before) begin
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$fatal(1, "illegal burst reached the word target");
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end
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end
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endtask
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task automatic issue_early_last_write(input logic [31:0] address);
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integer accesses_before;
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begin
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accesses_before = target_accesses;
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@(negedge clk_i);
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axi4.awaddr = address;
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axi4.awlen = 8'd3;
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axi4.awvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.awready);
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@(negedge clk_i);
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axi4.awvalid = 1'b0;
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axi4.wdata = 32'hDEAD_BEEF;
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axi4.wstrb = 4'hF;
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axi4.wlast = 1'b1;
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axi4.wvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.wready);
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@(negedge clk_i);
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axi4.wvalid = 1'b0;
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axi4.bready = 1'b1;
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do @(posedge clk_i); while (!axi4.bvalid);
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if (axi4.bresp != `AXI4_RESP_SLAVE_ERROR) begin
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$fatal(1, "early WLAST did not return SLVERR");
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end
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@(negedge clk_i);
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axi4.bready = 1'b0;
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axi4.wlast = 1'b0;
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if (target_accesses != accesses_before + 1) begin
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$fatal(1, "early WLAST must commit exactly one word beat");
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end
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end
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endtask
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task automatic issue_read(input logic [31:0] address, input logic [7:0] length);
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integer beat;
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begin
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = length;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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beat = 0;
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while (beat <= length) begin
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@(posedge clk_i);
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if (axi4.rvalid) begin
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if (axi4.rresp != `AXI4_RESP_OKAY || axi4.rlast != (beat == length)) begin
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$fatal(1, "performance read response mismatch");
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end
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beat = beat + 1;
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end
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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end
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endtask
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task automatic issue_address_pattern_read(input logic [31:0] address, input logic [7:0] length,
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input logic [1:0] burst);
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integer beat;
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logic [31:0] expected_address;
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logic [31:0] burst_bytes;
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begin
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burst_bytes = (length + 1) * 4;
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = length;
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axi4.arburst = burst;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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beat = 0;
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while (beat <= length) begin
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@(posedge clk_i);
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if (axi4.rvalid) begin
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if (burst == `AXI4_BURST_TYPE_FIXED) begin
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expected_address = address;
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end else begin
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expected_address = (address & ~(burst_bytes - 1)) |
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((address + (beat * 4)) & (burst_bytes - 1));
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end
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if (axi4.rdata != memory[expected_address[7:2]] ||
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axi4.rresp != `AXI4_RESP_OKAY || axi4.rlast != (beat == length)) begin
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$fatal(1, "address pattern mismatch beat=%0d addr=%08x data=%08x", beat,
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expected_address, axi4.rdata);
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end
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beat = beat + 1;
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end
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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end
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endtask
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initial begin
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init_axi4();
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for (int index = 0; index < 64; index++) memory[index] = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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issue_write4(32'h0000_0040);
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issue_read4(32'h0000_0040);
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for (int index = 0; index < 64; index++) memory[index] = 32'h5000_0000 + index;
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issue_address_pattern_read(32'h0000_0020, 8'd3, `AXI4_BURST_TYPE_FIXED);
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issue_address_pattern_read(32'h0000_002C, 8'd3, `AXI4_BURST_TYPE_WRAP);
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issue_illegal_read(32'h0000_0080);
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issue_early_last_write(32'h0000_00C0);
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burst_cycles = cycle_count;
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issue_read(32'h0000_0000, 8'd15);
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burst_cycles = cycle_count - burst_cycles;
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single_cycles = cycle_count;
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for (int index = 0; index < 16; index++) begin
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issue_read(32'(index * 4), 8'd0);
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end
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single_cycles = cycle_count - single_cycles;
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if ((burst_cycles * 5) > (single_cycles * 4)) begin
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$fatal(1, "16-beat burst improvement is below 20%%: burst=%0d single=%0d", burst_cycles,
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single_cycles);
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end
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if (target_accesses != 49) $fatal(1, "unexpected word access count");
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$display("AXI4 word bridge test passed");
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$finish;
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end
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endmodule
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