mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
e86187a5f3
- Added TCD head and count registers to DMA definition and register files. - Introduced CRC expected and result registers for enhanced error checking. - Updated DMA version to 2.0 to reflect new features. - Modified DMA testbench to validate new TCD and CRC functionalities. - Enhanced README and filelists to include new dependencies and configurations. - Updated formal verification and runtime tests to accommodate new DMA features.
270 lines
8.3 KiB
Systemverilog
270 lines
8.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module dma_reg_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic irq_o;
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logic xpi_done_o;
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logic read_active_q = 1'b0;
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logic write_active_q = 1'b0;
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logic write_response_q = 1'b0;
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logic allow_write_response = 1'b0;
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dma_req_if req ();
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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axi4_if axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_tx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if dvp_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_in_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_out_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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assign axi4.arready = !read_active_q;
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assign axi4.rid = '0;
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assign axi4.rdata = 32'hC0DE_0001;
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assign axi4.rresp = `AXI4_RESP_OKAY;
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assign axi4.rlast = 1'b1;
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assign axi4.ruser = '0;
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assign axi4.rvalid = read_active_q;
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assign axi4.awready = !write_active_q && !write_response_q;
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assign axi4.wready = write_active_q;
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assign axi4.bid = '0;
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assign axi4.bresp = `AXI4_RESP_OKAY;
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assign axi4.buser = '0;
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assign axi4.bvalid = write_response_q && allow_write_response;
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assign i2s_tx_axis.tready = 1'b0;
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assign i2s_rx_axis.tdata = '0;
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assign i2s_rx_axis.tkeep = '0;
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assign i2s_rx_axis.tstrb = '0;
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assign i2s_rx_axis.tlast = 1'b0;
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assign i2s_rx_axis.tid = '0;
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assign i2s_rx_axis.tdest = '0;
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assign i2s_rx_axis.tuser = '0;
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assign i2s_rx_axis.tvalid = 1'b0;
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assign dvp_rx_axis.tdata = '0;
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assign dvp_rx_axis.tkeep = '0;
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assign dvp_rx_axis.tstrb = '0;
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assign dvp_rx_axis.tlast = 1'b0;
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assign dvp_rx_axis.tid = '0;
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assign dvp_rx_axis.tdest = '0;
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assign dvp_rx_axis.tuser = '0;
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assign dvp_rx_axis.tvalid = 1'b0;
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assign crypto_in_axis.tready = 1'b0;
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assign crypto_out_axis.tdata = '0;
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assign crypto_out_axis.tkeep = '0;
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assign crypto_out_axis.tstrb = '0;
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assign crypto_out_axis.tlast = 1'b0;
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assign crypto_out_axis.tid = '0;
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assign crypto_out_axis.tdest = '0;
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assign crypto_out_axis.tuser = '0;
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assign crypto_out_axis.tvalid = 1'b0;
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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read_active_q <= 1'b0;
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write_active_q <= 1'b0;
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write_response_q <= 1'b0;
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end else begin
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if (axi4.arvalid && axi4.arready) begin
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if (axi4.arlen != 8'd0) begin
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$fatal(1, "register-directed transfer unexpectedly burst");
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end
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read_active_q <= 1'b1;
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end
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if (axi4.rvalid && axi4.rready) begin
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read_active_q <= 1'b0;
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end
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if (axi4.awvalid && axi4.awready) begin
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if (axi4.awlen != 8'd0) begin
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$fatal(1, "register-directed transfer unexpectedly burst");
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end
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write_active_q <= 1'b1;
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end
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if (axi4.wvalid && axi4.wready) begin
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if (!axi4.wlast || (axi4.wdata != 32'hC0DE_0001)) begin
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$fatal(1, "DMA register transfer write data mismatch");
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end
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write_active_q <= 1'b0;
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write_response_q <= 1'b1;
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end
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if (axi4.bvalid && axi4.bready) begin
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write_response_q <= 1'b0;
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end
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end
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end
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apb4_dma u_apb4_dma (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_o(xpi_done_o),
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.irq_o (irq_o),
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.hw_trg (req),
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.apb4 (apb4),
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.axi4 (axi4),
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.i2s_tx_axis (i2s_tx_axis),
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.i2s_rx_axis (i2s_rx_axis),
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.dvp_rx_axis (dvp_rx_axis),
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.crypto_in_axis (crypto_in_axis),
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.crypto_out_axis(crypto_out_axis)
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);
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task automatic apb_write(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe, input logic expected_error);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = strobe;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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#1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr != expected_error) begin
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$fatal(1, "APB write %h PSLVERR=%b expected=%b", address, apb4.pslverr, expected_error);
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end
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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task automatic apb_read(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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#1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr) begin
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$fatal(1, "APB read %h unexpectedly failed", address);
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end
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data = apb4.prdata;
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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initial begin
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logic [31:0] value;
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apb4.paddr = '0;
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apb4.pprot = '0;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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req.i2s_tx_proc = 1'b1;
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req.i2s_rx_proc = 1'b1;
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req.qspi_tx_proc = 1'b1;
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req.qspi_rx_proc = 1'b1;
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req.uart_tx_proc = 1'b1;
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req.uart_rx_proc = 1'b1;
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req.i2c0_tx_proc = 1'b1;
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req.i2c0_rx_proc = 1'b1;
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req.i2c1_tx_proc = 1'b1;
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req.i2c1_rx_proc = 1'b1;
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req.crypto_in_proc = 1'b1;
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req.crypto_out_proc = 1'b1;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_read(32'h000, value);
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if (value != 32'h444D_4134) begin
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$fatal(1, "DMA IP identification mismatch");
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end
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apb_read(32'h004, value);
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if (value != 32'h0002_0000) begin
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$fatal(1, "DMA V2 version mismatch: %h", value);
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end
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apb_read(32'h008, value);
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if ((value[0] != 1'b1) || (value[15:8] != 8'd4)) begin
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$fatal(1, "DMA capability descriptor/channel mismatch: %h", value);
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end
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apb_write(32'h2C8, 32'h4000_8000, 4'hF, 1'b0);
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apb_write(32'h2CC, 32'h0000_0001, 4'hF, 1'b0);
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apb_write(32'h2D0, 32'h1234_5678, 4'hF, 1'b0);
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apb_read(32'h2C8, value);
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if (value != 32'h4000_8000) begin
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$fatal(1, "DMA TCD head register mismatch: %h", value);
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end
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apb_read(32'h2D0, value);
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if (value != 32'h1234_5678) begin
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$fatal(1, "DMA CRC expected register mismatch: %h", value);
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end
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apb_write(32'h02c, 32'h1, 4'hF, 1'b1);
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apb_write(32'h104, 32'h0000_0160, 4'h1, 1'b0);
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apb_write(32'h108, 32'h4000_0000, 4'hF, 1'b0);
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apb_write(32'h10c, 32'h4000_1000, 4'hF, 1'b0);
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apb_write(32'h110, 32'h0000_0004, 4'hF, 1'b0);
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apb_write(32'h114, 32'h0000_0000, 4'hF, 1'b0);
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apb_write(32'h118, 32'h0000_0001, 4'hF, 1'b0);
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apb_write(32'h11c, 32'h0000_0007, 4'hF, 1'b0);
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apb_write(32'h018, 32'h0000_0001, 4'hF, 1'b0);
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apb_write(32'h100, 32'h0000_0001, 4'h1, 1'b0);
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wait (write_response_q);
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apb_write(32'h110, 32'h0000_0008, 4'hF, 1'b1);
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apb_write(32'h100, 32'h0000_0010, 4'h1, 1'b1);
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apb_write(32'h00c, 32'h0000_0001, 4'h1, 1'b1);
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apb_write(32'h100, 32'h0000_0001, 4'h2, 1'b1);
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allow_write_response = 1'b1;
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wait (!write_response_q);
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repeat (2) @(posedge clk_i);
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apb_read(32'h120, value);
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if ((value & 32'h0000_0005) != 32'h0000_0004) begin
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$fatal(1, "DMA status did not report a completed, idle transfer: %h", value);
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end
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apb_read(32'h124, value);
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if (((value & 32'h1) == 32'd0) || !irq_o) begin
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$fatal(1, "DMA done event did not assert the aggregate IRQ");
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end
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apb_write(32'h124, 32'h0000_0007, 4'h2, 1'b1);
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if (!irq_o) begin
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$fatal(1, "DMA event clear ignored unsupported PSTRB");
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end
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apb_write(32'h124, 32'h0000_0007, 4'h1, 1'b0);
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repeat (1) @(posedge clk_i);
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if (irq_o) begin
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$fatal(1, "DMA W1C event clear did not lower the aggregate IRQ");
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end
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apb_write(32'h00c, 32'h0000_0001, 4'h1, 1'b0);
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$display("DMA APB register and aggregate IRQ test passed");
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$finish;
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end
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endmodule
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