mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
324 lines
9.5 KiB
Systemverilog
324 lines
9.5 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "apb4_i2c_define.svh"
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module i2c_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic dma_tx_stall;
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logic dma_rx_stall;
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logic slave_scl_low = 1'b0;
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logic slave_sda_low = 1'b0;
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logic scl_line;
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logic sda_line;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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i2c_if i2c ();
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always #5 clk_i = ~clk_i;
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assign scl_line = (i2c.scl_oe_o || slave_scl_low) ? 1'b0 : 1'b1;
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assign sda_line = (i2c.sda_oe_o || slave_sda_low) ? 1'b0 : 1'b1;
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assign i2c.scl_i = scl_line;
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assign i2c.sda_i = sda_line;
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apb4_i2c u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(dma_tx_stall),
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.dma_rx_stall_o(dma_rx_stall),
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.apb4 (apb4),
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.i2c (i2c)
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);
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task automatic apb4_write(input logic [31:0] address, input logic [31:0] data,
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input logic expected_error);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== expected_error) begin
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$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, expected_error);
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end
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic apb4_read(input logic [31:0] address, input logic expected_error,
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output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== expected_error) begin
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$fatal(1, "read %h error=%b expected=%b", address, apb4.pslverr, expected_error);
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end
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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task automatic wait_start;
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begin
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@(negedge sda_line);
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while (!scl_line) begin
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@(negedge sda_line);
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end
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end
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endtask
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task automatic receive_byte(output logic [7:0] data, input integer stretch_cycles);
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integer bit_index;
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begin
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for (bit_index = 7; bit_index >= 0; bit_index = bit_index - 1) begin
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@(posedge scl_line);
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data[bit_index] = sda_line;
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end
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@(negedge scl_line);
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slave_sda_low = 1'b1;
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if (stretch_cycles != 0) begin
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slave_scl_low = 1'b1;
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repeat (stretch_cycles) @(posedge clk_i);
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slave_scl_low = 1'b0;
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end
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@(posedge scl_line);
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@(negedge scl_line);
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slave_sda_low = 1'b0;
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end
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endtask
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task automatic send_byte(input logic [7:0] data, output logic nack);
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integer bit_index;
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begin
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for (bit_index = 7; bit_index >= 0; bit_index = bit_index - 1) begin
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slave_sda_low = !data[bit_index];
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@(posedge scl_line);
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@(negedge scl_line);
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end
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slave_sda_low = 1'b0;
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@(posedge scl_line);
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nack = sda_line;
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@(negedge scl_line);
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end
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endtask
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task automatic wait_done;
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logic [31:0] value;
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logic [31:0] error_value;
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logic [31:0] status_value;
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integer attempts;
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begin
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value = '0;
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for (attempts = 0; attempts < 4000; attempts = attempts + 1) begin
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apb4_read(`APB4_I2C_INTR_STATE, 1'b0, value);
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if (value[`I2C_INTR_DONE]) begin
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attempts = 4000;
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end
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end
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if (!value[`I2C_INTR_DONE]) begin
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apb4_read(`APB4_I2C_ERROR_STATUS, 1'b0, error_value);
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apb4_read(`APB4_I2C_STATUS, 1'b0, status_value);
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$fatal(1, "I2C transaction did not complete: error=%h status=%h fsm=%0d", error_value,
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status_value, u_dut.u_i2c_core.s_fsm_q);
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end
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apb4_write(`APB4_I2C_INTR_STATE, 32'hFF, 1'b0);
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end
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endtask
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task automatic clear_state;
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begin
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apb4_write(`APB4_I2C_ERROR_STATUS, 32'h7FF, 1'b0);
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apb4_write(`APB4_I2C_INTR_STATE, 32'hFF, 1'b0);
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apb4_write(`APB4_I2C_COMMAND, 32'hC, 1'b0);
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end
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endtask
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initial begin
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logic [31:0] value;
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logic [ 7:0] byte_value;
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logic nack;
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integer pulse_count;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pprot = '0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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apb4_read(`APB4_I2C_IP_VERSION, 1'b0, value);
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if (value != 32'h0002_0000) $fatal(1, "I2C version mismatch");
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apb4_read(`APB4_I2C_CAPABILITY, 1'b0, value);
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if (value != 32'h007F_1010) $fatal(1, "I2C capability mismatch: %h", value);
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apb4_read(32'h2, 1'b1, value);
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apb4_write(`APB4_I2C_SCL_TIMING, 32'h0008_0008, 1'b0);
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apb4_write(`APB4_I2C_START_TIMING, 32'h0002_0002, 1'b0);
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apb4_write(`APB4_I2C_DATA_TIMING, 32'h0001_0000, 1'b0);
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apb4_write(`APB4_I2C_STOP_TIMING, 32'h0002_0002, 1'b0);
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apb4_write(`APB4_I2C_FILTER, 0, 1'b0);
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apb4_write(`APB4_I2C_STRETCH_TIMEOUT, 200, 1'b0);
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apb4_write(`APB4_I2C_BUS_IDLE_TIMEOUT, 200, 1'b0);
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apb4_write(`APB4_I2C_COMMAND_TIMEOUT, 2000, 1'b0);
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apb4_write(`APB4_I2C_TARGET_ADDR, 7'h50, 1'b0);
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apb4_write(`APB4_I2C_CTRL, 1, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA0) $fatal(1, "write address mismatch: %h", byte_value);
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA5) $fatal(1, "write data mismatch: %h", byte_value);
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end
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begin
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apb4_write(`APB4_I2C_DATA_CMD, 32'h4A5, 1'b0);
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wait_done();
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end
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join
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clear_state();
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apb4_write(`APB4_I2C_TARGET_ADDR, 32'h0000_06AA, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hF4) $fatal(1, "10-bit write header mismatch: %h", byte_value);
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receive_byte(byte_value, 0);
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if (byte_value != 8'hAA) $fatal(1, "10-bit low address mismatch: %h", byte_value);
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hF5) $fatal(1, "10-bit read header mismatch: %h", byte_value);
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send_byte(8'hC3, nack);
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if (!nack) $fatal(1, "final 10-bit read byte was not NACKed");
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end
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begin
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apb4_write(`APB4_I2C_DATA_CMD, 32'hD00, 1'b0);
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wait_done();
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apb4_read(`APB4_I2C_RXDATA, 1'b0, value);
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if (value[7:0] != 8'hC3) $fatal(1, "10-bit read data mismatch: %h", value);
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end
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join
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clear_state();
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apb4_write(`APB4_I2C_TARGET_ADDR, 7'h50, 1'b0);
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fork
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begin
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA0) $fatal(1, "combined write address mismatch");
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receive_byte(byte_value, 0);
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if (byte_value != 8'h12) $fatal(1, "combined register byte mismatch");
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wait_start();
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receive_byte(byte_value, 0);
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if (byte_value != 8'hA1) $fatal(1, "combined read address mismatch");
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send_byte(8'h5A, nack);
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if (!nack) $fatal(1, "final read byte was not NACKed");
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end
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begin
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apb4_write(`APB4_I2C_DATA_CMD, 32'h012, 1'b0);
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apb4_write(`APB4_I2C_DATA_CMD, 32'hF00, 1'b0);
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wait_done();
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apb4_read(`APB4_I2C_RXDATA, 1'b0, value);
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if (value[7:0] != 8'h5A) $fatal(1, "read data mismatch: %h", value);
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end
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join
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clear_state();
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fork
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begin
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wait_start();
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receive_byte(byte_value, 12);
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receive_byte(byte_value, 0);
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end
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begin
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apb4_write(`APB4_I2C_DATA_CMD, 32'h45C, 1'b0);
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wait_done();
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end
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join
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clear_state();
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apb4_write(`APB4_I2C_TARGET_ADDR, 7'h51, 1'b0);
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apb4_write(`APB4_I2C_DATA_CMD, 32'h455, 1'b0);
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repeat (300) @(posedge clk_i);
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apb4_read(`APB4_I2C_ERROR_STATUS, 1'b0, value);
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if (!value[`I2C_ERROR_ADDR_NACK]) $fatal(1, "address NACK was not reported");
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clear_state();
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apb4_write(`APB4_I2C_TARGET_ADDR, 7'h7F, 1'b0);
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fork
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begin
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wait_start();
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@(negedge scl_line);
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#1 slave_sda_low = 1'b1;
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@(posedge scl_line);
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repeat (4) @(posedge clk_i);
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slave_sda_low = 1'b0;
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end
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begin
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apb4_write(`APB4_I2C_DATA_CMD, 32'h400, 1'b0);
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end
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join
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repeat (20) @(posedge clk_i);
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apb4_read(`APB4_I2C_ERROR_STATUS, 1'b0, value);
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if (!value[`I2C_ERROR_ARB_LOST]) $fatal(1, "arbitration loss was not reported");
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clear_state();
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slave_sda_low = 1'b1;
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fork
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begin
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pulse_count = 0;
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while (pulse_count < 9) begin
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@(posedge scl_line);
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pulse_count = pulse_count + 1;
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end
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slave_sda_low = 1'b0;
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end
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begin
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apb4_write(`APB4_I2C_COMMAND, 32'h2, 1'b0);
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end
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join
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repeat (80) @(posedge clk_i);
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apb4_read(`APB4_I2C_INTR_STATE, 1'b0, value);
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if (!value[`I2C_INTR_RECOVERY_DONE] || (pulse_count != 9)) begin
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$fatal(1, "bus recovery failed: intr=%h pulses=%0d", value, pulse_count);
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end
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if (i2c.scl_o !== 1'b0 || i2c.sda_o !== 1'b0) begin
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$fatal(1, "I2C pads are not open-drain constants");
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end
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$display("I2C transfer, error, stretch, arbitration, and recovery test passed");
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$finish;
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end
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initial begin
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repeat (50000) @(posedge clk_i);
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$fatal(1, "I2C test timeout");
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end
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endmodule
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