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https://github.com/retroSoC/retroSoC.git
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- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge. - Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure. - Updated and modules to include JTAG interface signals. - Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB. - Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios. - Updated SDC generation to include JTAG clock domain and port requirements. - Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
14 lines
347 B
Makefile
14 lines
347 B
Makefile
SOC := MINI
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CORE := HAZARD3
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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PDK_BEHAV := YES
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HAVE_SVA := NO
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HAVE_DEBUG := YES
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ISA := RV32IM
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HAVE_CSR := NO
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APP := debug
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FIRMWARE_NAME := retrosoc_debug
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LINK_TYPE := ld2_sram
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