Files
retroSoC/configs/ci/ihp130-debug.mk
T
maksyuki 6cff6102a4 feat: add management debug reset and JTAG integration for Hazard3
- Implemented  module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created  to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated  and  modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
2026-08-05 22:30:11 +08:00

14 lines
347 B
Makefile

SOC := MINI
CORE := HAZARD3
PDK := IHP130
HAVE_PLL := NO
HAVE_SRAM_IF := YES
HAVE_SRAM_MACRO := YES
PDK_BEHAV := YES
HAVE_SVA := NO
HAVE_DEBUG := YES
ISA := RV32IM
HAVE_CSR := NO
APP := debug
FIRMWARE_NAME := retrosoc_debug
LINK_TYPE := ld2_sram