mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
70 lines
2.3 KiB
Python
70 lines
2.3 KiB
Python
"""UART register, FIFO, framing, flow-control, interrupt, and DMA tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_uart_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/serial"
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source_list = tmp_path / "uart.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'cdc'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{serial}",
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str(common / "interface/apb4_if.sv"),
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str(common / "cdc/cdc_sync.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/edge_det.sv"),
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str(common / "utils/fifo.sv"),
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str(serial / "uart_if.sv"),
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str(serial / "uart_baudgen.sv"),
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str(serial / "apb4_uart_tx.sv"),
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str(serial / "apb4_uart_rx.sv"),
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str(serial / "uart_flow_ctrl.sv"),
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str(serial / "uart_core.sv"),
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str(serial / "uart_reg.sv"),
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str(serial / "apb4_uart.sv"),
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str(ROOT / "tests/rtl/uart_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "uart_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "uart_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "uart_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "UART register, FIFO, loopback, flow-control, interrupt, and DMA test passed" in result.stdout
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