mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6bb5dc2344
- Updated RTL style audit to reflect new APB4 naming conventions. - Changed performance log parsing to accommodate new APB4 wait signals. - Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals. - Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths. - Updated sysctrl testbench to reflect changes in APB4 performance wait signals. - Refined memory map tests to check for new APB4 definitions. - Enhanced performance log tests to validate new APB4 wait signal parsing. - Revised SOC topology tests to ensure correct APB4 peripheral and system bindings. - Updated user extensions tests to align with new APB4 interface naming.
94 lines
3.0 KiB
Python
94 lines
3.0 KiB
Python
"""Tests for the machine-readable benchmark log parser."""
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from __future__ import annotations
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from scripts.parse_coremark_log import parse_log as parse_coremark_log
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from scripts.parse_performance_log import parse_log
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def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
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report = parse_log(
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"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
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"apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
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"PERF_BENCHMARK_PASS\n"
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)
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assert report["status"] == "passed"
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assert report["failure_marker"] is False
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assert report["pass_marker"] is True
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assert report["samples"] == [
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{
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"checksum": 0x1234,
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"cycles": 123,
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"dma_wait": 0,
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"flash_wait": 0,
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"mgmt_wait": 10,
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"apb4_periph_wait": 9,
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"operation": "read",
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"psram_wait": 0,
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"region": "sdram",
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"sdram_wait": 8,
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"words": 1024,
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}
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]
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def test_parse_log_rejects_missing_benchmark_marker() -> None:
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report = parse_log(
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"PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 apb4_periph_wait=1 "
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"sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
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)
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assert report["status"] == "failed"
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def test_parse_log_rejects_report_with_performance_failure() -> None:
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report = parse_log(
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"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
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"apb4_periph_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
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"PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
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"PERF_BENCHMARK_PASS\n"
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)
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assert report["status"] == "failed"
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assert report["failure_marker"] is True
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def test_parse_coremark_quick_report() -> None:
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report = parse_coremark_log(
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"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=2000 "
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"cpu_hz=72000000\nCOREMARK_PASS\n"
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)
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assert report["status"] == "passed"
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assert report["results"] == [
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{
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"coremark_per_mhz": "2000.000",
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"cpu_hz": 72000000,
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"cycles": 2000,
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"iterations": 4,
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"memory": "sram",
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"mode": "quick",
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"qualified": False,
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}
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]
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def test_parse_coremark_rejects_failure_or_non_sram_result() -> None:
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report = parse_coremark_log(
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"COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=36 cycles=1800 "
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"cpu_hz=72000000\nCOREMARK_FAIL result=1\n"
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)
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assert report["status"] == "failed"
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assert report["failure_marker"] is True
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try:
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parse_coremark_log(
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"COREMARK_RESULT mode=quick qualified=0 memory=psram iterations=36 cycles=1800 "
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"cpu_hz=72000000\nCOREMARK_PASS\n"
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)
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except ValueError as error:
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assert "SRAM" in str(error)
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else:
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raise AssertionError("non-SRAM CoreMark result was accepted")
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