mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
142 lines
4.6 KiB
Python
142 lines
4.6 KiB
Python
"""SDRAM controller data-integrity regression."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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generated = tmp_path / "generated"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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],
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check=True,
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)
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source_list = tmp_path / "sdram_data.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{generated / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
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str(ROOT / "rtl/mini/dv/verilator/rtl/sdram_verilator_model.sv"),
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str(ROOT / "tests/rtl/sdram_data_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "sdram_data_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "sdram_data_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "sdram_data_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "sdram data integrity test passed" in result.stdout
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def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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generated = tmp_path / "generated"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(generated),
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],
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check=True,
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)
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source_list = tmp_path / "sdram_timing.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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"+define+SDRAM_TIMING_MODEL",
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f"+incdir+{generated / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
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str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
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str(ROOT / "tests/rtl/sdram_data_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "sdram_timing_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "sdram_timing_tb"
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-s",
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"sdram_data_tb",
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"-I",
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str(ROOT / "rtl/managed/third_party/model/sdram"),
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"-o",
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str(simulation),
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str(converted),
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str(ROOT / "rtl/managed/third_party/model/sdram/sdr.v"),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "sdram data integrity test passed" in result.stdout
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