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maksyuki dd3cb6ff5c feat: add formal verification properties for DMA design and corresponding testbench

- Introduced  to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created  as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added  to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.

2026-08-18 16:54:55 +08:00

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

rtl

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

README.md

chore: enhance RTL style checks and enforce naming conventions

2026-08-13 12:01:38 +08:00

test_axi4.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_clint.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_clock_reset_domains.py

feat: add RTC wake functionality and related integration

2026-08-10 09:32:30 +08:00

test_dma_register_parity.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_dma.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_dvp.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_gpio.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_i2c.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_i2s.py

feat: add I2S support with formal verification and testbench

2026-08-17 15:53:39 +08:00

test_memory_map.py

refactor: refactor APB4 and AXI4 references in RTL and test files

2026-08-17 12:38:43 +08:00

test_mgmt_debug.py

feat: add management debug reset and JTAG integration for Hazard3

2026-08-05 22:30:11 +08:00

test_performance_log.py

refactor: refactor APB4 and AXI4 references in RTL and test files

2026-08-17 12:38:43 +08:00

test_pin_map.py

refactor: remove HAVE_DEBUG feature and related code

2026-08-06 08:52:54 +08:00

test_psram.py

refactor: refactor PSRAM register module for improved signal handling and add new signals

2026-08-17 17:17:43 +08:00

test_repository_layout.py

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

test_rib2apb.py

feat: refactor RIB to APB bridge and update related components

2026-08-05 16:03:41 +08:00

test_rib.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_rtl_connection_migration.py

style: refactor error handling in rib modules and improve RTL naming conventions

2026-08-12 22:18:19 +08:00

test_rtl_readiness.py

feat: add RTL readiness checks and validation scripts for synthesis intent

2026-08-13 10:59:33 +08:00

test_rtl_style.py

refactor: refactor RTL style checker and update test cases

2026-08-15 08:33:27 +08:00

test_script_tools.py

feat: enhance SDRAM Controller and Testbench Functionality

2026-08-18 09:06:19 +08:00

test_sdram.py

feat: enhance SDRAM Controller and Testbench Functionality

2026-08-18 09:06:19 +08:00

test_soc_topology.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_sta_constraints.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_sysctrl.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_tech_cell_config.py

feat: refactor NMI interface and remove unused variables

2026-07-26 09:03:33 +08:00

test_timer.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_uart.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_user_extensions.py

refactor: refactor APB4 and AXI4 references in RTL and test files

2026-08-17 12:38:43 +08:00

test_ws2812.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_xpi_io.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_yosys_synth_recipes.py

refactor: refactor Yosys synthesis flow to support multiple recipes

2026-08-17 08:54:57 +08:00

README.md

Repository Tests

This directory contains tests for deterministic SDK behavior and build/quality tooling.

c/test_runtime.c is the host C test program used by make sw-host-test.
test_script_tools.py covers setup, dependency, filelist, warning, metric, archive, and regression-helper behavior.
test_rtl_readiness.py covers the machine-readable RTL maturity and synthesis-intent checks.
test_rtl_style.py covers ownership, named connections, and staged naming rules for new owned RTL.

Add a host C test when changing deterministic runtime or media logic; add a Python test when changing scripts or build policy. Run:

make sw-host-test
python3 -m pytest -q

These tests complement, but do not replace, firmware builds, RTL simulation, synthesis, timing, or hardware validation.