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maksyuki
3b6a925a51
- Created documentation for , , , and modules, detailing their functionality, parameters, and usage examples. - Implemented a script to ensure required headings and content are present in documentation files. - Developed to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
95 lines
3.2 KiB
Markdown
95 lines
3.2 KiB
Markdown
# cdc_2phase
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| Property | Value |
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| --- | --- |
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| Kind | `module` |
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| RTL source | [`rtl/cdc/cdc_2phase.sv`](../../../rtl/cdc/cdc_2phase.sv) |
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| Availability | Synthesizable RTL |
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## Summary
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Two-phase asynchronous request/acknowledge transfer.
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## Functional Behavior
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Two-phase asynchronous request/acknowledge transfer. It carries the declared control, event, or data contract through the stated synchronizer, handshake, or Gray-pointer mechanism. Endpoint reset discards in-flight data unless the page identifies an acknowledged warm-clear path.
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## Suitable Applications
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Use for reset release, asynchronous control/data transfer, asynchronous queues, event notification, and CDC recovery.
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## Parameters
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The declaration below is canonical; retain the RTL-enforced parameter range.
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| Parameter | Declaration |
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| --- | --- |
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| `DATA_WIDTH` | `parameter int DATA_WIDTH = 32` |
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| `SYNC_STAGES` | `parameter int SYNC_STAGES = 2` |
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## Interface Definition
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```systemverilog
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module cdc_2phase #(
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parameter int DATA_WIDTH = 32,
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parameter int SYNC_STAGES = 2
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) (
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input logic src_clk_i,
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input logic src_rst_n_i,
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input logic [DATA_WIDTH-1:0] src_data_i,
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input logic src_valid_i,
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output logic src_ready_o,
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input logic dst_clk_i,
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input logic dst_rst_n_i,
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output logic [DATA_WIDTH-1:0] dst_data_o,
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output logic dst_valid_o,
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input logic dst_ready_i
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);
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```
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### Port Summary
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| Signal | Direction | Declaration |
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| --- | --- | --- |
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| `src_clk_i` | `input` | `input logic src_clk_i` |
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| `src_rst_n_i` | `input` | `input logic src_rst_n_i` |
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| `src_data_i` | `input` | `input logic [DATA_WIDTH-1:0] src_data_i` |
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| `src_valid_i` | `input` | `input logic src_valid_i` |
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| `src_ready_o` | `output` | `output logic src_ready_o` |
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| `dst_clk_i` | `input` | `input logic dst_clk_i` |
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| `dst_rst_n_i` | `input` | `input logic dst_rst_n_i` |
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| `dst_data_o` | `output` | `output logic [DATA_WIDTH-1:0] dst_data_o` |
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| `dst_valid_o` | `output` | `output logic dst_valid_o` |
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| `dst_ready_i` | `input` | `input logic dst_ready_i` |
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## Integration and Use
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Never use a simple synchronizer for arbitrary multi-bit data. Keep both endpoint clocks running after reset release and obey all ready/busy outputs.
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```systemverilog
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cdc_2phase #(
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.DATA_WIDTH(DATA_WIDTH),
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.SYNC_STAGES(SYNC_STAGES)
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) u_cdc_2phase (
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.src_clk_i(src_clk_i),
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.src_rst_n_i(src_rst_n_i),
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.src_data_i(src_data_i),
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.src_valid_i(src_valid_i),
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.src_ready_o(src_ready_o),
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.dst_clk_i(dst_clk_i),
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.dst_rst_n_i(dst_rst_n_i),
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.dst_data_o(dst_data_o),
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.dst_valid_o(dst_valid_o),
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.dst_ready_i(dst_ready_i)
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);
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```
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## Dependencies and Verification
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The linked RTL source is the implementation authority and contains local assertions for unsupported
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parameter combinations. See [`docs/design.md`](../../design.md) for repository-wide CDC, reset,
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stream, and storage contracts, and [`docs/verification.md`](../../verification.md) for the
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verification matrix.
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