admin/retroSoC
1
0 Fork 0
mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-06 14:55:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat: refactor RIB to RIBP: Update tests and scripts to reflect RIBP interface changes

Browse Source 
- Updated test cases in , , , , , , , and  to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
This commit is contained in:
maksyuki committed 2026-08-04 10:56:36 +08:00
1 parent bef5881149
commit 1b4b53c650
139 files changed
+3363 -3217
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

tests/rtl/bus_fault_tb.sv
+33 -33
View File
@@ -11,35 +11,35 @@ module bus_fault_tb;
logic [ 1:0] fault_master_o;
logic [ 2:0] fault_code_o;
logic user_bus_idle_o;
soc_rib_if mgmt_rib ();
soc_rib_burst_if user_rib ();
soc_rib_burst_if dma_rib ();
soc_rib_burst_if rib ();
rib_if apb_rib ();
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if apb_ribp ();
always #5 clk_i = ~clk_i;
assign rib.cmd_ready = 1'b1;
assign rib.w_ready = 1'b1;
assign rib.rsp_valid = 1'b0;
assign rib.rdata = 32'hCAFE_BABE;
assign rib.resp_err = 1'b0;
assign rib.resp_code = `SOC_RIB_RESP_OK;
assign rib.rsp_beat = '0;
assign rib.rsp_last = 1'b0;
assign apb_rib.ready = 1'b1;
assign apb_rib.rdata = 32'h1234_5678;
assign rib.cmd_ready = 1'b1;
assign rib.w_ready = 1'b1;
assign rib.rsp_valid = 1'b0;
assign rib.rdata = 32'hCAFE_BABE;
assign rib.resp_err = 1'b0;
assign rib.resp_code = `SOC_RIB_RESP_OK;
assign rib.rsp_beat = '0;
assign rib.rsp_last = 1'b0;
assign apb_ribp.ready = 1'b1;
assign apb_ribp.rdata = 32'h1234_5678;
bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_rib (mgmt_rib),
.mgmt_ribl (mgmt_ribl),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_rib (apb_rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
@@ -56,22 +56,22 @@ module bus_fault_tb;
input logic reserved, input logic [2:0] expected_code);
begin
@(negedge clk_i);
mgmt_rib.addr = address;
mgmt_rib.wdata = 32'hA5A5_5A5A;
mgmt_rib.wstrb = write_strobes;
mgmt_rib.valid = 1'b1;
mgmt_ribl.addr = address;
mgmt_ribl.wdata = 32'hA5A5_5A5A;
mgmt_ribl.wstrb = write_strobes;
mgmt_ribl.valid = 1'b1;
while (!fault_valid_o) @(posedge clk_i);
if (fault_addr_o !== address || fault_wstrb_o !== write_strobes ||
fault_reserved_o !== reserved || fault_access_o || fault_code_o !== expected_code ||
rib.cmd_valid || apb_rib.valid) begin
rib.cmd_valid || apb_ribp.valid) begin
$fatal(1, "unexpected fault response for address %h", address);
end
while (!mgmt_rib.ready) @(posedge clk_i);
if (mgmt_rib.rdata !== 32'd0 || !mgmt_rib.resp_err) begin
while (!mgmt_ribl.ready) @(posedge clk_i);
if (mgmt_ribl.rdata !== 32'd0 || !mgmt_ribl.resp_err) begin
$fatal(1, "fault response data must be zero");
end
@(negedge clk_i);
mgmt_rib.valid = 1'b0;
mgmt_ribl.valid = 1'b0;
while (fault_valid_o) @(posedge clk_i);
end
endtask
@@ -81,7 +81,7 @@ module bus_fault_tb;
@(negedge clk_i);
user_rib.cmd_addr = address;
user_rib.cmd_write = |write_strobes;
user_rib.cmd_len = `SOC_RIB_BURST_INCR1;
user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
user_rib.cmd_valid = 1'b1;
while (!user_rib.cmd_ready) @(posedge clk_i);
@(negedge clk_i);
@@ -96,7 +96,7 @@ module bus_fault_tb;
user_rib.w_valid = 1'b0;
end
while (!fault_valid_o) @(posedge clk_i);
if (!fault_access_o || fault_master_o != 2'd1 || rib.cmd_valid || apb_rib.valid) begin
if (!fault_access_o || fault_master_o != 2'd1 || rib.cmd_valid || apb_ribp.valid) begin
$fatal(1, "user access was not denied locally");
end
if (user_rib.rdata !== 32'd0 || !user_rib.resp_err || !user_rib.rsp_last ||
@@ -108,14 +108,14 @@ module bus_fault_tb;
endtask
initial begin
mgmt_rib.valid = 1'b0;
mgmt_rib.addr = '0;
mgmt_rib.wdata = '0;
mgmt_rib.wstrb = '0;
mgmt_ribl.valid = 1'b0;
mgmt_ribl.addr = '0;
mgmt_ribl.wdata = '0;
mgmt_ribl.wstrb = '0;
user_rib.cmd_valid = 1'b0;
user_rib.cmd_addr = '0;
user_rib.cmd_write = 1'b0;
user_rib.cmd_len = `SOC_RIB_BURST_INCR1;
user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
user_rib.w_valid = 1'b0;
user_rib.wdata = '0;
user_rib.wstrb = '0;
@@ -124,7 +124,7 @@ module bus_fault_tb;
dma_rib.cmd_valid = 1'b0;
dma_rib.cmd_addr = '0;
dma_rib.cmd_write = 1'b0;
dma_rib.cmd_len = `SOC_RIB_BURST_INCR1;
dma_rib.cmd_len = `SOC_RIB_LEN_INCR1;
dma_rib.w_valid = 1'b0;
dma_rib.wdata = '0;
dma_rib.wstrb = '0;
tests/rtl/dma_error_tb.sv
+3 -3
View File
@@ -33,7 +33,7 @@ module dma_error_tb;
logic model_write_q = 1'b0;
logic model_error_q = 1'b0;
dma_hw_trg_if hw_trg ();
soc_rib_burst_if rib ();
soc_rib_if rib ();
always #5 clk_i = ~clk_i;
@@ -63,10 +63,10 @@ module dma_error_tb;
model_write_q <= rib.cmd_write;
model_error_q <= error_mode && !rib.cmd_write;
model_state_q <= rib.cmd_write ? MODEL_WDATA : MODEL_RESP;
if (rib.cmd_len == `SOC_RIB_BURST_INCR4 && rib.cmd_write) begin
if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && rib.cmd_write) begin
incr4_write_count <= incr4_write_count + 1;
end
if (rib.cmd_len == `SOC_RIB_BURST_INCR4 && !rib.cmd_write) begin
if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && !rib.cmd_write) begin
incr4_read_count <= incr4_read_count + 1;
end
end
tests/rtl/gpio_user_mux_tb.sv
+3 -3
View File
@@ -3,17 +3,17 @@
module gpio_user_mux_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
rib_if rib ();
ribp_if rib ();
gpio_if gpio ();
user_gpio_if user_gpio ();
logic [31:0] read_data;
always #5 clk_i = ~clk_i;
rib_gpio dut (
ribp_gpio dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.rib (rib),
.ribp (rib),
.gpio (gpio),
.user_gpio(user_gpio)
);
tests/rtl/pll_ctrl_tb.sv
+3 -3
View File
@@ -9,7 +9,7 @@ module pll_ctrl_tb;
logic [31:0] fault_addr_i = '0;
logic [ 3:0] fault_wstrb_i = '0;
logic fault_reserved_i = 1'b0;
rib_if rib ();
ribp_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
logic sys_clk_o;
@@ -38,14 +38,14 @@ module pll_ctrl_tb;
.sys_clkdiv4_o(sys_clkdiv4_o)
);
rib_sysctrl u_sysctrl (
ribp_sysctrl u_sysctrl (
.clk_i (sys_clk_o),
.rst_n_i (sys_rst_n_o),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.rib (rib),
.ribp (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
tests/rtl/rib_burst_bus_tb.sv → tests/rtl/rib_bus_tb.sv
+20 -20
View File
@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module rib_burst_bus_tb;
module rib_bus_tb;
localparam logic TARGET_IDLE = 1'b0;
localparam logic TARGET_RESP = 1'b1;
@@ -16,11 +16,11 @@ module rib_burst_bus_tb;
logic fault_valid_o;
logic [2:0] fault_code_o;
logic user_bus_idle_o;
soc_rib_if mgmt_rib ();
soc_rib_burst_if user_rib ();
soc_rib_burst_if dma_rib ();
soc_rib_burst_if rib ();
rib_if apb_rib ();
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if apb_ribp ();
always #5 clk_i = ~clk_i;
always @(posedge clk_i) cycle_count <= cycle_count + 1;
@@ -57,19 +57,19 @@ module rib_burst_bus_tb;
end
end
assign apb_rib.ready = apb_rib.valid;
assign apb_rib.rdata = 32'h1234_5678;
assign apb_ribp.ready = apb_ribp.valid;
assign apb_ribp.rdata = 32'h1234_5678;
bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_rib (mgmt_rib),
.mgmt_ribl (mgmt_ribl),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_rib (apb_rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
@@ -83,7 +83,7 @@ module rib_burst_bus_tb;
.perf_mgmt_wait_o (),
.perf_user_wait_o (),
.perf_dma_wait_o (),
.perf_rib_wait_o (),
.perf_ribp_wait_o (),
.perf_apb_wait_o (),
.perf_sdram_wait_o(),
.perf_psram_wait_o(),
@@ -130,10 +130,10 @@ module rib_burst_bus_tb;
endtask
initial begin
mgmt_rib.valid = 1'b0;
mgmt_rib.addr = '0;
mgmt_rib.wdata = '0;
mgmt_rib.wstrb = '0;
mgmt_ribl.valid = 1'b0;
mgmt_ribl.addr = '0;
mgmt_ribl.wdata = '0;
mgmt_ribl.wstrb = '0;
user_rib.cmd_valid = 1'b0;
user_rib.cmd_addr = '0;
user_rib.cmd_write = 1'b0;
@@ -156,15 +156,15 @@ module rib_burst_bus_tb;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
issue_read(32'h3800_1000, `SOC_RIB_BURST_INCR4, 1'b0);
issue_read(32'h3800_1000, `SOC_RIB_LEN_INCR4, 1'b0);
if (rib_command_count != 1) begin
$fatal(1, "INCR4 was split before reaching the burst RIB target");
end
issue_read(32'h3800_1004, `SOC_RIB_BURST_INCR4, 1'b1);
issue_read(32'h1000_0000, `SOC_RIB_BURST_INCR4, 1'b1);
issue_read(32'h2000_0000, `SOC_RIB_BURST_INCR4, 1'b1);
issue_read(32'h3800_1004, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h1000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h2000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h3800_1000, 2'd2, 1'b1);
if (rib_command_count != 1 || apb_rib.valid) begin
if (rib_command_count != 1 || apb_ribp.valid) begin
$fatal(1, "illegal burst reached a downstream target");
end
tests/rtl/sdram_data_tb.sv
+3 -3
View File
@@ -5,7 +5,7 @@ module sdram_data_tb;
logic rst_n_i = 1'b0;
wire [15:0] s_dq;
logic [31:0] s_read_data;
rib_if rib ();
ribp_if rib ();
sdram_if sdram ();
always #5 clk_i = ~clk_i;
@@ -13,10 +13,10 @@ module sdram_data_tb;
assign s_dq = sdram.oe_o ? sdram.dq_o : 'z;
assign sdram.dq_i = s_dq;
rib_sdram u_rib_sdram (
ribp_sdram u_ribp_sdram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (rib),
.ribp (rib),
.sdram (sdram)
);
tests/rtl/soc_irq_topology_tb.sv
+8 -8
View File
@@ -4,7 +4,7 @@
module soc_irq_topology_tb;
logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
logic [ `SOC_IRQ_RIB_WIDTH-1:0] s_rib_irq;
logic [ `SOC_IRQ_RIBP_WIDTH-1:0] s_ribp_irq;
logic [ `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
`include "soc_irq_wiring.svh"
@@ -19,19 +19,19 @@ module soc_irq_topology_tb;
endtask
initial begin
s_rib_irq = '0;
s_apb_irq = '0;
s_ribp_irq = '0;
s_apb_irq = '0;
expect_irq('0);
for (int bit_index = 0; bit_index < `SOC_IRQ_RIB_WIDTH; bit_index++) begin
s_rib_irq = '0;
s_rib_irq[bit_index] = 1'b1;
s_apb_irq = '0;
for (int bit_index = 0; bit_index < `SOC_IRQ_RIBP_WIDTH; bit_index++) begin
s_ribp_irq = '0;
s_ribp_irq[bit_index] = 1'b1;
s_apb_irq = '0;
expect_irq(32'd1 << bit_index);
end
for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
s_rib_irq = '0;
s_ribp_irq = '0;
s_apb_irq = '0;
s_apb_irq[bit_index] = 1'b1;
expect_irq(32'd1 << (10 + bit_index));
tests/rtl/soc_rib_burst_ram_tb.sv → tests/rtl/soc_rib_ram_tb.sv
+43 -43
View File
@@ -1,12 +1,12 @@
`timescale 1ns / 1ps
module soc_rib_burst_ram_tb;
module soc_rib_ram_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
logic [31:0] memory [0:31];
logic [31:0] expected [ 0:3];
integer index;
soc_rib_burst_if burst ();
soc_rib_if rib ();
ram_if ram ();
always #5 clk_i = ~clk_i;
@@ -19,23 +19,23 @@ module soc_rib_burst_ram_tb;
if (ram.wstrb[3]) memory[ram.addr][31:24] <= ram.wdata[31:24];
end
soc_rib_burst_ram u_dut (
soc_rib_ram u_dut (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.burst (burst),
.rib (rib),
.ram (ram)
);
task automatic issue_command(input logic write);
begin
@(negedge clk_i);
burst.cmd_addr = 32'h3000_0000;
burst.cmd_write = write;
burst.cmd_len = `SOC_RIB_BURST_INCR4;
burst.cmd_valid = 1'b1;
while (!burst.cmd_ready) @(posedge clk_i);
rib.cmd_addr = 32'h3000_0000;
rib.cmd_write = write;
rib.cmd_len = `SOC_RIB_LEN_INCR4;
rib.cmd_valid = 1'b1;
while (!rib.cmd_ready) @(posedge clk_i);
@(negedge clk_i);
burst.cmd_valid = 1'b0;
rib.cmd_valid = 1'b0;
end
endtask
@@ -44,15 +44,15 @@ module soc_rib_burst_ram_tb;
for (index = 0; index < 4; index = index + 1) begin
expected[index] = 32'hA500_1000 + index;
end
burst.cmd_valid = 1'b0;
burst.cmd_addr = '0;
burst.cmd_write = 1'b0;
burst.cmd_len = '0;
burst.w_valid = 1'b0;
burst.wdata = '0;
burst.wstrb = '0;
burst.wlast = 1'b0;
burst.rsp_ready = 1'b1;
rib.cmd_valid = 1'b0;
rib.cmd_addr = '0;
rib.cmd_write = 1'b0;
rib.cmd_len = '0;
rib.w_valid = 1'b0;
rib.wdata = '0;
rib.wstrb = '0;
rib.wlast = 1'b0;
rib.rsp_ready = 1'b1;
repeat (2) @(posedge clk_i);
@(negedge clk_i);
@@ -60,60 +60,60 @@ module soc_rib_burst_ram_tb;
issue_command(1'b1);
for (index = 0; index < 4; index = index + 1) begin
burst.w_valid = 1'b1;
burst.wdata = expected[index];
burst.wstrb = 4'hF;
burst.wlast = index == 3;
while (!burst.w_ready) @(posedge clk_i);
rib.w_valid = 1'b1;
rib.wdata = expected[index];
rib.wstrb = 4'hF;
rib.wlast = index == 3;
while (!rib.w_ready) @(posedge clk_i);
@(negedge clk_i);
end
burst.w_valid = 1'b0;
burst.wlast = 1'b0;
while (!burst.rsp_valid) @(posedge clk_i);
if (burst.resp_err || !burst.rsp_last || burst.rsp_beat != 2'd3) begin
rib.w_valid = 1'b0;
rib.wlast = 1'b0;
while (!rib.rsp_valid) @(posedge clk_i);
if (rib.resp_err || !rib.rsp_last || rib.rsp_beat != 2'd3) begin
$fatal(1, "invalid SRAM write response");
end
@(negedge clk_i);
burst.rsp_ready = 1'b0;
rib.rsp_ready = 1'b0;
issue_command(1'b0);
while (!burst.rsp_valid) @(negedge clk_i);
burst.rsp_ready = 1'b1;
while (!rib.rsp_valid) @(negedge clk_i);
rib.rsp_ready = 1'b1;
for (index = 0; index < 4; index = index + 1) begin
if (burst.rdata !== expected[index] || burst.rsp_beat !== index[1:0] ||
burst.rsp_last !== (index == 3) || burst.resp_err) begin
if (rib.rdata !== expected[index] || rib.rsp_beat !== index[1:0] ||
rib.rsp_last !== (index == 3) || rib.resp_err) begin
$fatal(1, "invalid SRAM read response beat=%0d data=%h expected=%h rsp_beat=%0d last=%0b",
index, burst.rdata, expected[index], burst.rsp_beat, burst.rsp_last);
index, rib.rdata, expected[index], rib.rsp_beat, rib.rsp_last);
end
@(posedge clk_i);
@(negedge clk_i);
if ((index != 3) && !burst.rsp_valid) begin
if ((index != 3) && !rib.rsp_valid) begin
$fatal(1, "SRAM inserted a response bubble at beat %0d", index + 1);
end
end
burst.rsp_ready = 1'b0;
rib.rsp_ready = 1'b0;
issue_command(1'b0);
while (!burst.rsp_valid) @(negedge clk_i);
while (!rib.rsp_valid) @(negedge clk_i);
repeat (4) begin
@(posedge clk_i);
if (!burst.rsp_valid || burst.rdata !== expected[0] || burst.rsp_beat != 2'd0) begin
if (!rib.rsp_valid || rib.rdata !== expected[0] || rib.rsp_beat != 2'd0) begin
$fatal(1, "SRAM response changed while stalled");
end
end
@(negedge clk_i);
burst.rsp_ready = 1'b1;
rib.rsp_ready = 1'b1;
for (index = 0; index < 4; index = index + 1) begin
if (burst.rdata !== expected[index] || burst.rsp_beat !== index[1:0]) begin
if (rib.rdata !== expected[index] || rib.rsp_beat !== index[1:0]) begin
$fatal(1, "SRAM lost data after backpressure beat=%0d data=%h rsp_beat=%0d", index,
burst.rdata, burst.rsp_beat);
rib.rdata, rib.rsp_beat);
end
@(posedge clk_i);
@(negedge clk_i);
while ((index != 3) && !burst.rsp_valid) @(negedge clk_i);
while ((index != 3) && !rib.rsp_valid) @(negedge clk_i);
end
$display("RIB burst SRAM pipeline test passed");
$display("RIB SRAM pipeline test passed");
$finish;
end
endmodule
tests/rtl/soc_topology_rib_tb.sv
-112
View File
@@ -1,112 +0,0 @@
`timescale 1ns / 1ps
`include "mmap_define.svh"
module soc_topology_rib_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
rib_if rib ();
`include "soc_rib_interfaces.svh"
`include "soc_rib_routes.svh"
always #5 clk_i = ~clk_i;
task automatic expect_route(input logic [31:0] address, input integer slot,
input logic [31:0] expected_rdata);
begin
@(negedge clk_i);
rib.addr = address;
rib.valid = 1'b1;
#1;
if (s_slv_sel_d !== (18'd1 << slot)) begin
$fatal(1, "unexpected target slot for %h", address);
end
@(posedge clk_i);
#1;
if (!rib.ready || rib.rdata !== expected_rdata) begin
$fatal(1, "unexpected response for %h", address);
end
@(negedge clk_i);
rib.valid = 1'b0;
@(posedge clk_i);
end
endtask
task automatic expect_disabled(input logic [31:0] address);
begin
@(negedge clk_i);
rib.addr = address;
rib.valid = 1'b1;
#1;
if (s_slv_sel_d !== '0) begin
$fatal(1, "disabled target accepted %h", address);
end
@(posedge clk_i);
#1;
if (rib.ready || rib.rdata !== '0) begin
$fatal(1, "disabled target responded to %h", address);
end
@(negedge clk_i);
rib.valid = 1'b0;
@(posedge clk_i);
end
endtask
initial begin
rib.valid = 1'b0;
rib.addr = '0;
rib.wdata = '0;
rib.wstrb = '0;
u_uart_rib_if.ready = 1'b1;
u_gpio_rib_if.ready = 1'b1;
u_tim0_rib_if.ready = 1'b1;
u_tim1_rib_if.ready = 1'b1;
u_psram_rib_if.ready = 1'b1;
u_spisd_rib_if.ready = 1'b1;
u_i2c0_rib_if.ready = 1'b1;
u_i2s_rib_if.ready = 1'b1;
u_onewire_rib_if.ready = 1'b1;
u_xpi_rib_if.ready = 1'b1;
u_dma_rib_if.ready = 1'b1;
u_sysctrl_rib_if.ready = 1'b1;
u_clint_rib_if.ready = 1'b1;
u_sdram_rib_if.ready = 1'b1;
u_dvp_rib_if.ready = 1'b1;
u_sdio_rib_if.ready = 1'b1;
u_opipsram_rib_if.ready = 1'b1;
u_i2c1_rib_if.ready = 1'b1;
u_uart_rib_if.rdata = 32'h0000_0000;
u_gpio_rib_if.rdata = 32'h1111_1111;
u_tim0_rib_if.rdata = 32'h2222_2222;
u_tim1_rib_if.rdata = 32'h3333_3333;
u_psram_rib_if.rdata = 32'h4444_4444;
u_spisd_rib_if.rdata = 32'h5555_5555;
u_i2c0_rib_if.rdata = 32'h6666_6666;
u_i2s_rib_if.rdata = 32'h7777_7777;
u_onewire_rib_if.rdata = 32'h8888_8888;
u_xpi_rib_if.rdata = 32'h9999_9999;
u_dma_rib_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_rib_if.rdata = 32'hBBBB_BBBB;
u_clint_rib_if.rdata = 32'hCCCC_CCCC;
u_sdram_rib_if.rdata = 32'hDDDD_DDDD;
u_dvp_rib_if.rdata = 32'hEEEE_EEEE;
u_sdio_rib_if.rdata = 32'hF0F0_F0F0;
u_opipsram_rib_if.rdata = 32'h0F0F_0F0F;
u_i2c1_rib_if.rdata = 32'h1234_5678;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_route(`SOC_ADDR_RIB_GPIO_BASE, 1, 32'h1111_1111);
expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
expect_route(`SOC_ADDR_RIB_I2C1_BASE, 17, 32'h1234_5678);
expect_disabled(`SOC_ADDR_RIB_SDIO_BASE);
$display("SoC topology RIB routing test passed");
$finish;
end
endmodule
tests/rtl/soc_topology_ribp_tb.sv
+112
View File
@@ -0,0 +1,112 @@
`timescale 1ns / 1ps
`include "mmap_define.svh"
module soc_topology_ribp_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
ribp_if ribp ();
`include "soc_ribp_interfaces.svh"
`include "soc_ribp_routes.svh"
always #5 clk_i = ~clk_i;
task automatic expect_route(input logic [31:0] address, input integer slot,
input logic [31:0] expected_rdata);
begin
@(negedge clk_i);
ribp.addr = address;
ribp.valid = 1'b1;
#1;
if (s_slv_sel_d !== (18'd1 << slot)) begin
$fatal(1, "unexpected target slot for %h", address);
end
@(posedge clk_i);
#1;
if (!ribp.ready || ribp.rdata !== expected_rdata) begin
$fatal(1, "unexpected response for %h", address);
end
@(negedge clk_i);
ribp.valid = 1'b0;
@(posedge clk_i);
end
endtask
task automatic expect_disabled(input logic [31:0] address);
begin
@(negedge clk_i);
ribp.addr = address;
ribp.valid = 1'b1;
#1;
if (s_slv_sel_d !== '0) begin
$fatal(1, "disabled target accepted %h", address);
end
@(posedge clk_i);
#1;
if (ribp.ready || ribp.rdata !== 32'd0) begin
$fatal(1, "disabled target responded to %h", address);
end
@(negedge clk_i);
ribp.valid = 1'b0;
@(posedge clk_i);
end
endtask
initial begin
ribp.valid = 1'b0;
ribp.addr = '0;
ribp.wdata = '0;
ribp.wstrb = '0;
u_uart_ribp_if.ready = 1'b1;
u_gpio_ribp_if.ready = 1'b1;
u_tim0_ribp_if.ready = 1'b1;
u_tim1_ribp_if.ready = 1'b1;
u_psram_ribp_if.ready = 1'b1;
u_spisd_ribp_if.ready = 1'b1;
u_i2c0_ribp_if.ready = 1'b1;
u_i2s_ribp_if.ready = 1'b1;
u_onewire_ribp_if.ready = 1'b1;
u_xpi_ribp_if.ready = 1'b1;
u_dma_ribp_if.ready = 1'b1;
u_sysctrl_ribp_if.ready = 1'b1;
u_clint_ribp_if.ready = 1'b1;
u_sdram_ribp_if.ready = 1'b1;
u_dvp_ribp_if.ready = 1'b1;
u_sdio_ribp_if.ready = 1'b1;
u_opipsram_ribp_if.ready = 1'b1;
u_i2c1_ribp_if.ready = 1'b1;
u_uart_ribp_if.rdata = 32'h0000_0000;
u_gpio_ribp_if.rdata = 32'h1111_1111;
u_tim0_ribp_if.rdata = 32'h2222_2222;
u_tim1_ribp_if.rdata = 32'h3333_3333;
u_psram_ribp_if.rdata = 32'h4444_4444;
u_spisd_ribp_if.rdata = 32'h5555_5555;
u_i2c0_ribp_if.rdata = 32'h6666_6666;
u_i2s_ribp_if.rdata = 32'h7777_7777;
u_onewire_ribp_if.rdata = 32'h8888_8888;
u_xpi_ribp_if.rdata = 32'h9999_9999;
u_dma_ribp_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_ribp_if.rdata = 32'hBBBB_BBBB;
u_clint_ribp_if.rdata = 32'hCCCC_CCCC;
u_sdram_ribp_if.rdata = 32'hDDDD_DDDD;
u_dvp_ribp_if.rdata = 32'hEEEE_EEEE;
u_sdio_ribp_if.rdata = 32'hF0F0_F0F0;
u_opipsram_ribp_if.rdata = 32'h0F0F_0F0F;
u_i2c1_ribp_if.rdata = 32'h1234_5678;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_route(`SOC_ADDR_RIBP_GPIO_BASE, 1, 32'h1111_1111);
expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
expect_route(`SOC_ADDR_RIBP_I2C1_BASE, 17, 32'h1234_5678);
expect_disabled(`SOC_ADDR_RIBP_SDIO_BASE);
$display("SoC topology RIBP routing test passed");
$finish;
end
endmodule
tests/rtl/spill_register_tb.sv
+6 -2
View File
@@ -39,7 +39,7 @@ module spill_register_tb;
task automatic check_cycle;
begin
@(posedge clk_i);
if (held_valid && (!valid_o || (data_o !== held_data))) begin
if (held_valid && !flush_i && (!valid_o || (data_o !== held_data))) begin
$fatal(1, "spill register changed output while stalled");
end
if (valid_o && ready_i) begin
@@ -83,9 +83,13 @@ module spill_register_tb;
@(negedge clk_i);
end
valid_i = 1'b0;
valid_i = 1'b1;
data_i = 32'hDEAD_BEEF;
flush_i = 1'b1;
check_cycle();
if (valid_o || ready_o) begin
$fatal(1, "spill register accepted a transfer while flushing");
end
@(negedge clk_i);
flush_i = 1'b0;
tests/rtl/sysctrl_fault_tb.sv
+4 -4
View File
@@ -7,20 +7,20 @@ module sysctrl_fault_tb;
logic [31:0] fault_addr_i = '0;
logic [ 3:0] fault_wstrb_i = '0;
logic fault_reserved_i = 1'b0;
rib_if rib ();
ribp_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
always #5 clk_i = ~clk_i;
rib_sysctrl u_sysctrl (
ribp_sysctrl u_sysctrl (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.rib (rib),
.ribp (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
@@ -67,7 +67,7 @@ module sysctrl_fault_tb;
sysctrl.perf_mgmt_wait_i = 64'd11;
sysctrl.perf_user_wait_i = 64'd12;
sysctrl.perf_dma_wait_i = 64'd13;
sysctrl.perf_rib_wait_i = 64'd14;
sysctrl.perf_ribp_wait_i = 64'd14;
sysctrl.perf_apb_wait_i = 64'd15;
sysctrl.perf_sdram_wait_i = 64'd16;
sysctrl.perf_psram_wait_i = 64'd17;
tests/test_dma.py
+4 -4
View File
@@ -39,13 +39,13 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
f"+incdir+{memory_map / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
str(ROOT / "rtl/ip/rib/peripheral/dma.sv"),
str(ROOT / "rtl/ip/rib/peripheral/dma_core.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/dma_core.sv"),
str(ROOT / "tests/rtl/dma_error_tb.sv"),
"",
]
tests/test_gpio_user_mux.py
+3 -3
View File
@@ -23,13 +23,13 @@ def test_user_ip_can_own_rib_gpio_pads_with_a_safe_handoff(tmp_path: Path) -> No
"\n".join(
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{ROOT / 'rtl/ip/rib/peripheral'}",
f"+incdir+{ROOT / 'rtl/ip/ribp/peripheral'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
str(ROOT / "rtl/ip/rib/peripheral/gpio.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/gpio.sv"),
str(ROOT / "tests/rtl/gpio_user_mux_tb.sv"),
"",
]
tests/test_memory_map.py
+20 -19
View File
@@ -58,13 +58,13 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
assert "RS_SOC_PSRAM_SIZE UINT32_C(0x00800000)" in header
assert "RS_SOC_SDRAM_SIZE UINT32_C(0x02000000)" in header
assert "RS_SOC_SPISD_SIZE UINT32_C(0x40000000)" in header
assert "RS_SOC_RIB_SDIO_BASE" not in header
assert "RS_SOC_RIBP_SDIO_BASE" not in header
assert "RS_SOC_NMI_" not in header
assert "RS_SOC_OPIPSRAM_BASE" not in header
assert "RS_SOC_HAS_SRAM 1U" in header
assert "SOC_SYSCTRL_PLL_CFG_OFFSET 32'h00000008" in rtl
assert "SOC_SYSCTRL_PLL_STATUS_OFFSET 32'h0000001C" in rtl
assert "SOC_ADDR_IS_RIB(addr)" in rtl
assert "SOC_ADDR_IS_RIBP(addr)" in rtl
assert "SOC_ADDR_IS_NMI" not in rtl
assert "RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)" in header
assert "RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)" in header
@@ -112,16 +112,16 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P
f"+incdir+{tmp_path / 'rtl'}",
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_rib_legacy_to_burst.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_to_legacy.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_ram.sv"),
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib_ram.sv"),
str(ROOT / "rtl/mini/top/bus.sv"),
str(ROOT / "tests/rtl/bus_fault_tb.sv"),
"",
@@ -172,11 +172,11 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/rib/peripheral/sysctrl.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
"",
]
@@ -221,14 +221,15 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"),
str(ROOT / "rtl/ip/rib/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/rib/peripheral/sysctrl.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
str(ROOT / "rtl/tech/tc_clk.sv"),
str(ROOT / "rtl/tech/tc_pll.sv"),
str(ROOT / "rtl/mini/top/rcu.sv"),
@@ -299,12 +300,12 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
rtl = (ROOT / "rtl/ip/rib/peripheral/sysctrl.sv").read_text(encoding="utf-8")
rtl = (ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv").read_text(encoding="utf-8")
header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
for symbol in (
"RIB_SYSCTRL_I2CSEL",
"RIB_SYSCTRL_QSPISEL",
"SYSCTRL_I2CSEL",
"SYSCTRL_QSPISEL",
"i2c_sel_o",
"qspi_sel_o",
"s_sysctrl_i2csel",
tests/test_performance_log.py
+4 -4
View File
@@ -8,7 +8,7 @@ from scripts.parse_performance_log import parse_log
def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"ribp_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_BENCHMARK_PASS\n"
)
@@ -22,7 +22,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
"dma_wait": 0,
"flash_wait": 0,
"mgmt_wait": 10,
"rib_wait": 9,
"ribp_wait": 9,
"operation": "read",
"psram_wait": 0,
"region": "sdram",
@@ -34,7 +34,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
def test_parse_log_rejects_missing_benchmark_marker() -> None:
report = parse_log(
"PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 rib_wait=1 "
"PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 ribp_wait=1 "
"sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
)
@@ -44,7 +44,7 @@ def test_parse_log_rejects_missing_benchmark_marker() -> None:
def test_parse_log_rejects_report_with_performance_failure() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"ribp_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
"PERF_BENCHMARK_PASS\n"
)
tests/test_rib_burst.py → tests/test_rib.py
+20 -20
View File
@@ -1,4 +1,4 @@
"""Directed tests for the SoC-owned RIB burst building blocks."""
"""Directed tests for the SoC-owned RIB building blocks."""
from __future__ import annotations
@@ -31,7 +31,7 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
],
check=True,
)
source_list = tmp_path / "rib_burst_bus.fl"
source_list = tmp_path / "rib_bus.fl"
source_list.write_text(
"\n".join(
[
@@ -39,24 +39,24 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
f"+incdir+{memory_map / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_rib_legacy_to_burst.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_to_legacy.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_ram.sv"),
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib_ram.sv"),
str(ROOT / "rtl/mini/top/bus.sv"),
str(ROOT / "tests/rtl/rib_burst_bus_tb.sv"),
str(ROOT / "tests/rtl/rib_bus_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "rib_burst_bus_tb.v"
converted = tmp_path / "rib_bus_tb.v"
subprocess.run(
[
sys.executable,
@@ -68,9 +68,9 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
],
check=True,
)
simulation = tmp_path / "rib_burst_bus_tb"
simulation = tmp_path / "rib_bus_tb"
subprocess.run(
[iverilog, "-g2012", "-s", "rib_burst_bus_tb", "-o", str(simulation), str(converted)],
[iverilog, "-g2012", "-s", "rib_bus_tb", "-o", str(simulation), str(converted)],
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
@@ -107,7 +107,7 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
if iverilog is None or vvp is None:
return
source_list = tmp_path / "soc_rib_burst_ram.fl"
source_list = tmp_path / "soc_rib_ram.fl"
source_list.write_text(
"\n".join(
[
@@ -115,17 +115,17 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_rib_burst_ram.sv"),
str(ROOT / "tests/rtl/soc_rib_burst_ram_tb.sv"),
str(ROOT / "rtl/mini/top/soc_rib_ram.sv"),
str(ROOT / "tests/rtl/soc_rib_ram_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "soc_rib_burst_ram_tb.v"
converted = tmp_path / "soc_rib_ram_tb.v"
subprocess.run(
[
sys.executable,
@@ -137,10 +137,10 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
],
check=True,
)
simulation = tmp_path / "soc_rib_burst_ram_tb"
simulation = tmp_path / "soc_rib_ram_tb"
subprocess.run(
[iverilog, "-g2012", "-s", "soc_rib_burst_ram_tb", "-o", str(simulation), str(converted)],
[iverilog, "-g2012", "-s", "soc_rib_ram_tb", "-o", str(simulation), str(converted)],
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
assert "RIB burst SRAM pipeline test passed" in result.stdout
assert "RIB SRAM pipeline test passed" in result.stdout
tests/test_script_tools.py
+69 -19
View File
@@ -32,6 +32,7 @@ from scripts.check_c_warnings import self_owned_warnings # noqa: E402
from scripts.check_format import format_files # noqa: E402
from scripts.dependency_lock import LockError, load_lock # noqa: E402
from scripts.generate_mpw import ( # noqa: E402
migrate_user_core_ribp_interfaces,
migrate_user_extension_includes,
migrate_user_gpio_interfaces,
remove_legacy_picorv32_entry,
@@ -181,7 +182,7 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
bus_filelist = tmp_path / "bus.fl"
rib_adapter_filelist = tmp_path / "rib_adapter.fl"
spill_register_filelist = tmp_path / "spill_register.fl"
rib2apb_filelist = tmp_path / "rib2apb.fl"
rib2apb_filelist = tmp_path / "ribp2apb.fl"
sysctrl_filelist = tmp_path / "sysctrl.fl"
pll_rcu_filelist = tmp_path / "pll_rcu.fl"
gpio_user_filelist = tmp_path / "gpio_user.fl"
@@ -193,7 +194,7 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
"spill_register", spill_register_filelist, memory_map, topology, user_extensions
)
assert generate_formal_filelist(
"rib2apb", rib2apb_filelist, memory_map, topology, user_extensions
"ribp2apb", rib2apb_filelist, memory_map, topology, user_extensions
)
assert generate_formal_filelist(
"sysctrl", sysctrl_filelist, memory_map, topology, user_extensions
@@ -208,31 +209,31 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
bus = parse_filelists([bus_filelist], require_files=False)
rib_adapter = parse_filelists([rib_adapter_filelist], require_files=False)
spill_register = parse_filelists([spill_register_filelist], require_files=False)
rib2apb = parse_filelists([rib2apb_filelist], require_files=False)
ribp2apb = parse_filelists([rib2apb_filelist], require_files=False)
sysctrl = parse_filelists([sysctrl_filelist], require_files=False)
pll_rcu = parse_filelists([pll_rcu_filelist], require_files=False)
gpio_user = parse_filelists([gpio_user_filelist], require_files=False)
assert "+define+SV_ASSRT_DISABLE" in bus.defines
assert ROOT / "rtl/mini/top/bus.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_burst_if.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_legacy_to_burst.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_burst_error_slave.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_if.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_ribl2rib.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_error_slave.sv" in bus.files
assert ROOT / "rtl/mini/formal/bus_formal.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_burst_to_legacy.sv" in rib_adapter.files
assert ROOT / "rtl/mini/top/soc_rib2ribp.sv" in rib_adapter.files
assert ROOT / "rtl/mini/formal/rib_adapter_formal.sv" in rib_adapter.files
assert (
ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"
in spill_register.files
)
assert ROOT / "rtl/mini/formal/spill_register_formal.sv" in spill_register.files
assert ROOT / "rtl/ip/rib/interconnect/rib2apb.sv" in rib2apb.files
assert ROOT / "rtl/mini/formal/rib2apb_formal.sv" in rib2apb.files
assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in rib2apb.files
assert ROOT / "rtl/ip/rib/peripheral/sysctrl.sv" in sysctrl.files
assert ROOT / "rtl/ip/ribp/interconnect/ribp2apb.sv" in ribp2apb.files
assert ROOT / "rtl/mini/formal/ribp2apb_formal.sv" in ribp2apb.files
assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in ribp2apb.files
assert ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv" in sysctrl.files
assert ROOT / "rtl/mini/formal/sysctrl_formal.sv" in sysctrl.files
assert ROOT / "rtl/mini/top/rcu.sv" in pll_rcu.files
assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv" in pll_rcu.files
assert ROOT / "rtl/ip/rib/peripheral/gpio.sv" in gpio_user.files
assert ROOT / "rtl/ip/ribp/peripheral/gpio.sv" in gpio_user.files
assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in gpio_user.files
assert ROOT / "rtl/mini/formal/gpio_user_formal.sv" in gpio_user.files
@@ -267,7 +268,7 @@ def test_fatfs_release_script_uses_the_locked_archive_contract() -> None:
def test_formal_result_summary_requires_every_passing_step(tmp_path: Path) -> None:
proofs = ("bus", "rib2apb", "sysctrl", "pll_rcu", "gpio_user")
proofs = ("bus", "ribp2apb", "sysctrl", "pll_rcu", "gpio_user")
for proof in proofs:
directory = tmp_path / proof
directory.mkdir()
@@ -289,7 +290,7 @@ def test_formal_result_summary_requires_every_passing_step(tmp_path: Path) -> No
"--proof",
f"bus={tmp_path / 'bus'}",
"--proof",
f"rib2apb={tmp_path / 'rib2apb'}",
f"ribp2apb={tmp_path / 'ribp2apb'}",
"--proof",
f"sysctrl={tmp_path / 'sysctrl'}",
"--proof",
@@ -332,6 +333,27 @@ endmodule
assert "gpio.di_i" in migrated
def test_user_core_ribp_interface_is_migrated_in_generated_source(tmp_path: Path) -> None:
source = tmp_path / "user_core_design.sv"
source.write_text(
"""module user_core_design (rib_if.master rib);
ahbl2rib u_bridge (ahbl, rib);
assign rib.addr = 32'h0;
endmodule
""",
encoding="utf-8",
)
assert migrate_user_core_ribp_interfaces(tmp_path) == [source]
migrated = source.read_text(encoding="utf-8")
assert "rib_if" not in migrated
assert "ribp_if.master ribp" in migrated
assert "ahbl2ribp" in migrated
assert "ahbl, ribp" in migrated
assert "ribp.addr" in migrated
def test_generated_user_core_filelist_excludes_the_legacy_picorv32_entry(
tmp_path: Path,
) -> None:
@@ -523,7 +545,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
Path("Makefile"),
Path("configs/ci/example.mk"),
Path("rtl/mini/top/retrosoc.sv"),
Path("rtl/ip/rib/peripheral/sysctrl.sv"),
Path("rtl/ip/ribp/peripheral/sysctrl.sv"),
Path("rtl/tech/tc_clk.sv"),
Path("rtl/demo/reference.v"),
Path("rtl/managed/clusterip/common/rtl/utils/register.sv"),
@@ -537,7 +559,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
]
assert format_files(paths, "rtl") == [
Path("rtl/demo/reference.v"),
Path("rtl/ip/rib/peripheral/sysctrl.sv"),
Path("rtl/ip/ribp/peripheral/sysctrl.sv"),
Path("rtl/mini/top/retrosoc.sv"),
Path("rtl/tech/tc_clk.sv"),
]
@@ -639,7 +661,7 @@ def test_management_core_selection_is_limited_to_hazard3_and_picorv32() -> None:
assert "DEF_LIST += +define+CORE_$(CORE)" in makefile
assert "`ifdef CORE_PICORV32" in wrapper
assert "`elsif CORE_HAZARD3" in wrapper
assert "ahbl2soc_rib u_ahbl2soc_rib" in wrapper
assert "ahbl2soc_ribl u_ahbl2soc_rib" in wrapper
assert ".RESET_VECTOR (`SOC_CPU_RESET_ADDR)" in wrapper
@@ -722,8 +744,28 @@ def test_regression_observations_do_not_block_or_skip_metrics(
) -> None:
calls: list[list[str]] = []
monkeypatch.setattr(regress, "select_regression", lambda _suite, _pdk: ((), ("unit-profile",)))
monkeypatch.setattr(
regress,
"select_regression",
lambda _suite, _pdk: (
(("unit-profile", ("rtl-lint",)),),
("unit-profile",),
),
)
monkeypatch.setattr(regress, "regression_environment", lambda: {})
monkeypatch.setattr(regress, "self_owned_warnings", lambda _root, _output: [])
strict_calls: list[list[str]] = []
def pass_blocking_check(
command: list[str], root: Path, capture_output: bool, environment: dict[str, str]
) -> str:
assert root == tmp_path
assert capture_output is False
assert environment == {}
strict_calls.append(command)
return ""
monkeypatch.setattr(regress, "run_command", pass_blocking_check)
def fail_quality_check(
command: list[str], *, cwd: Path, env: dict[str, str], check: bool
@@ -742,11 +784,19 @@ def test_regression_observations_do_not_block_or_skip_metrics(
)
assert regress.main() == 0
assert strict_calls == [["make", "CONFIG=unit-profile", "rtl-lint"]]
assert calls == [
[
"make",
"CONFIG=unit-profile",
"SIMU=VERILATOR",
"HAVE_SVA=YES",
"check-rtl-lint",
],
["make", "CONFIG=unit-profile", "check-warnings"],
["make", "CONFIG=unit-profile", "check-metrics"],
]
assert capsys.readouterr().err.count("non-blocking observation failed") == 2
assert capsys.readouterr().err.count("non-blocking observation failed") == 3
def test_rtl_lint_warning_baseline_is_independent(tmp_path: Path) -> None:
tests/test_sdram.py
+10 -10
View File
@@ -36,12 +36,12 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
str(ROOT / "rtl/mini/dv/verilator/rtl/sdram_verilator_model.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
@@ -97,12 +97,12 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/ribp/memory/sdram_core.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
]
tests/test_soc_topology.py
+41 -41
View File
@@ -57,8 +57,8 @@ def write_invalid_topology(tmp_path: Path, document: dict[str, object]) -> Path:
def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -> None:
generate(tmp_path)
interfaces = (tmp_path / "rtl/soc_rib_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/soc_rib_routes.svh").read_text(encoding="utf-8")
interfaces = (tmp_path / "rtl/soc_ribp_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/soc_ribp_routes.svh").read_text(encoding="utf-8")
gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
@@ -67,35 +67,35 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
rib_irq = (tmp_path / "rtl/soc_rib_irq_bindings.svh").read_text(encoding="utf-8")
rib_irq = (tmp_path / "rtl/soc_ribp_irq_bindings.svh").read_text(encoding="utf-8")
apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
filelist = (tmp_path / "soc_topology.fl").read_text(encoding="utf-8")
assert interfaces.count("rib_if u_") == 18
assert interfaces.count("ribp_if u_") == 18
assert "nmi_if" not in interfaces
assert "soc_nmi" not in interfaces
assert "assign s_slv_sel_d[17] = u_i2c1_rib_if.valid;" in routes
assert "assign s_xpi_region_sel[1] = (rib.addr <= `SOC_ADDR_FLASH_END);" in routes
assert "assign u_sdio_rib_if.valid = 1'b0;" in routes
assert "assign s_slv_sel_d[17] = u_i2c1_ribp_if.valid;" in routes
assert "assign s_xpi_region_sel[1] = (ribp.addr <= `SOC_ADDR_FLASH_END);" in routes
assert "assign u_sdio_ribp_if.valid = 1'b0;" in routes
assert gpio.count("// GPIO") == 64
assert "assign u_uart1_if.rx_i = u_gpio_if.di_i[0];" in gpio
assert "assign u_gpio_if.alt1_do_i[22] = u_psram_if.nss_o[0];" in gpio
assert apb_interfaces.count("apb4_if u_") == 10
assert "apb4_pure_if u_archinfo_apb_pure_if ();" in apb_interfaces
assert "assign tmr.paddr = rib.addr;" in apb_routes
assert "assign tmr.paddr = ribp.addr;" in apb_routes
assert "({32{s_psel_q[8]}} & tmr.prdata)" in apb_response
assert "localparam int NSLV = 10;" in apb_declarations
assert fabric.count("soc_rib_if u_") == 1
assert fabric.count("soc_rib_burst_if u_") == 3
assert fabric.count("rib_if u_") == 2
assert ".mgmt_rib(u_mgmt_rib_if)" in bus_fabric
assert fabric.count("soc_ribl_if u_") == 1
assert fabric.count("soc_rib_if u_") == 3
assert fabric.count("ribp_if u_") == 1
assert ".mgmt_ribl(u_mgmt_ribl_if)" in bus_fabric
assert ".user_rib(u_user_rib_if)" in bus_fabric
assert ".apb_rib(u_apb_rib_if)" in bus_fabric
assert ".apb_ribp(u_apb_ribp_if)" in bus_fabric
assert ".rib(u_rib_if)" in bus_fabric
assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
assert "`define SOC_IRQ_RIB_WIDTH 10" in irq_config
assert "`define SOC_IRQ_RIBP_WIDTH 10" in irq_config
assert "`define SOC_IRQ_APB_WIDTH 7" in irq_config
assert "assign irq_o[0] = u_clint_if.sfr_irq_o;" in rib_irq
assert "assign irq_o[5] = u_tmr_if.irq_o;" in apb_irq
@@ -119,16 +119,16 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
for interrupt in document["interrupts"]
]
assert mappings[:17] == [
("clint_software", "rib", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "rib", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "rib", 2, 2, "uart.irq_o"),
("timer0", "rib", 3, 3, "s_tim0_irq"),
("timer1", "rib", 4, 4, "s_tim1_irq"),
("psram", "rib", 5, 5, "psram.irq_o"),
("spisd", "rib", 6, 6, "spisd.irq_o"),
("i2c0", "rib", 7, 7, "i2c0.irq_o"),
("i2s", "rib", 8, 8, "i2s.irq_o"),
("xpi", "rib", 9, 9, "xpi.irq_o"),
("clint_software", "ribp", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "ribp", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "ribp", 2, 2, "uart.irq_o"),
("timer0", "ribp", 3, 3, "s_tim0_irq"),
("timer1", "ribp", 4, 4, "s_tim1_irq"),
("psram", "ribp", 5, 5, "psram.irq_o"),
("spisd", "ribp", 6, 6, "spisd.irq_o"),
("i2c0", "ribp", 7, 7, "i2c0.irq_o"),
("i2s", "ribp", 8, 8, "i2s.irq_o"),
("xpi", "ribp", 9, 9, "xpi.irq_o"),
("uart1", "apb", 0, 10, "uart.irq_o"),
("pwm", "apb", 1, 11, "pwm.irq_o"),
("ps2", "apb", 2, 12, "ps2.irq_o"),
@@ -146,8 +146,8 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
formal_design = (ROOT / "rtl/mini/formal/rib2apb_formal.sv").read_text(encoding="utf-8")
formal_properties = (ROOT / "rtl/mini/formal/rib2apb_formal_props.v").read_text(
formal_design = (ROOT / "rtl/mini/formal/ribp2apb_formal.sv").read_text(encoding="utf-8")
formal_properties = (ROOT / "rtl/mini/formal/ribp2apb_formal_props.v").read_text(
encoding="utf-8"
)
@@ -162,27 +162,27 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["rib_targets"][0]["regions"] = ["UNKNOWN"]
document["ribp_targets"][0]["regions"] = ["UNKNOWN"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "unknown region" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["rib_targets"][0]["regions"] = ["SRAM"]
document["ribp_targets"][0]["regions"] = ["SRAM"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "not an active rib region" in result.stderr
assert "not an active RIBP region" in result.stderr
def test_topology_rejects_duplicate_region_and_disabled_owner(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["rib_targets"][1]["regions"] = ["RIB_UART0"]
document["ribp_targets"][1]["regions"] = ["RIBP_UART0"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "multiple targets" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["rib_targets"][15]["regions"] = ["RIB_SDIO"]
document["ribp_targets"][15]["regions"] = ["RIBP_SDIO"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "disabled but declares regions" in result.stderr
@@ -230,16 +230,16 @@ def test_topology_rejects_invalid_gpio_coverage_and_expression(tmp_path: Path) -
def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["irq_groups"][1]["name"] = "rib"
document["irq_groups"][1]["name"] = "ribp"
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "interrupt group rib is duplicated" in result.stderr
assert "interrupt group ribp is duplicated" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["interrupts"][1]["group_bit"] = 0
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "interrupt group rib bit 0 is duplicated" in result.stderr
assert "interrupt group ribp bit 0 is duplicated" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["interrupts"][1]["core_bit"] = 0
@@ -317,7 +317,7 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
topology_output = tmp_path / "topology"
generate(topology_output)
source_list = tmp_path / "soc_topology_rib.fl"
source_list = tmp_path / "soc_topology_ribp.fl"
source_list.write_text(
"\n".join(
[
@@ -325,15 +325,15 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
f"+incdir+{memory_map_output / 'rtl'}",
f"+incdir+{topology_output / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "tests/rtl/soc_topology_rib_tb.sv"),
str(ROOT / "tests/rtl/soc_topology_ribp_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "soc_topology_rib_tb.v"
converted = tmp_path / "soc_topology_ribp_tb.v"
subprocess.run(
[
sys.executable,
@@ -345,13 +345,13 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
],
check=True,
)
simulation = tmp_path / "soc_topology_rib_tb"
simulation = tmp_path / "soc_topology_ribp_tb"
subprocess.run(
[
iverilog,
"-g2012",
"-s",
"soc_topology_rib_tb",
"soc_topology_ribp_tb",
"-o",
str(simulation),
str(converted),
@@ -359,4 +359,4 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
assert "SoC topology RIB routing test passed" in result.stdout
assert "SoC topology RIBP routing test passed" in result.stdout
tests/test_sta_constraints.py
+1 -1
View File
@@ -49,7 +49,7 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
assert "create_clock -name clk_audio -period 54.253472222" in sdc
assert "create_clock -name clk_dvp -period 41.666666667" in sdc
assert "get_pins -quiet" in sdc
assert "u_retrosoc.u_ip_rib_wrapper/u_rib_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
assert "u_retrosoc.u_ip_ribp_wrapper.u_rib_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
assert "-group [get_clocks {clk_external clk_system}]" in sdc
assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
assert "set_input_transition" not in sdc
tests/test_user_extensions.py
+4 -4
View File
@@ -48,9 +48,9 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
assert core.count("soc_rib_burst_if u_user_") == 6
assert core.count("rib_if u_user_") == 6
assert core.count("rib_legacy_to_burst #(") == 6
assert core.count("soc_rib_if u_user_") == 6
assert core.count("ribp_if u_user_") == 6
assert core.count("ribp2rib #(") == 6
assert core.count(".SYNC_RESET(1'b1)") == 2
assert core.count(".SYNC_RESET(1'b0)") == 4
assert "rib.cmd_valid = '0;" in core
@@ -58,7 +58,7 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
assert "5'd5: begin" in core
assert "core_reset_i[0]" in core
assert "user_core_design_username1 #(" in core
assert "User core 0 uses the legacy RIB contract" in core
assert "User core 0 uses the RIBP contract" in core
assert ip.count("user_gpio_if #(`USER_GPIO_NUM)") == 2
assert "gpio.do_o = '0;" in ip
assert "8'd2: begin" in ip
tests/test_xpi_io.py
+5 -5
View File
@@ -35,13 +35,13 @@ def test_xpi_releases_data_pads_while_receiving(tmp_path: Path) -> None:
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/ip/rib/storage'}",
f"+incdir+{ROOT / 'rtl/ip/ribp/storage'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/rib/storage/xpi.sv"),
str(ROOT / "rtl/ip/rib/storage/xpi_clkgen.sv"),
str(ROOT / "rtl/ip/rib/storage/xpi_core.sv"),
str(ROOT / "rtl/ip/ribp/storage/xpi.sv"),
str(ROOT / "rtl/ip/ribp/storage/xpi_clkgen.sv"),
str(ROOT / "rtl/ip/ribp/storage/xpi_core.sv"),
str(ROOT / "tests/rtl/xpi_io_tb.sv"),
"",
]