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feat: refactor NMI to RIB Interface and Update Related Tests

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- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
This commit is contained in:
maksyuki committed 2026-08-02 15:57:08 +08:00
1 parent 0a6055134e
commit c5dfa96c6f
134 files changed
+3130 -3336
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tests/rtl/bus_fault_tb.sv
+46 -46
View File
@@ -11,29 +11,29 @@ module bus_fault_tb;
logic [ 1:0] fault_master_o;
logic [ 2:0] fault_code_o;
logic user_bus_idle_o;
soc_nmi_if mgmt_nmi ();
soc_nmi_if user_nmi ();
soc_nmi_if dma_nmi ();
nmi_if natv_nmi ();
nmi_if apb_nmi ();
soc_rib_if mgmt_rib ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
rib_if rib ();
rib_if apb_rib ();
always #5 clk_i = ~clk_i;
assign natv_nmi.ready = 1'b1;
assign natv_nmi.rdata = 32'hCAFE_BABE;
assign apb_nmi.ready = 1'b1;
assign apb_nmi.rdata = 32'h1234_5678;
assign rib.ready = 1'b1;
assign rib.rdata = 32'hCAFE_BABE;
assign apb_rib.ready = 1'b1;
assign apb_rib.rdata = 32'h1234_5678;
bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_nmi (mgmt_nmi),
.user_nmi (user_nmi),
.dma_nmi (dma_nmi),
.mgmt_rib (mgmt_rib),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.natv_nmi (natv_nmi),
.apb_nmi (apb_nmi),
.rib (rib),
.apb_rib (apb_rib),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
@@ -50,23 +50,23 @@ module bus_fault_tb;
input logic reserved, input logic [2:0] expected_code);
begin
@(negedge clk_i);
mgmt_nmi.addr = address;
mgmt_nmi.wdata = 32'hA5A5_5A5A;
mgmt_nmi.wstrb = write_strobes;
mgmt_nmi.valid = 1'b1;
mgmt_rib.addr = address;
mgmt_rib.wdata = 32'hA5A5_5A5A;
mgmt_rib.wstrb = write_strobes;
mgmt_rib.valid = 1'b1;
while (!fault_valid_o) @(posedge clk_i);
if (fault_addr_o !== address || fault_wstrb_o !== write_strobes ||
fault_reserved_o !== reserved || fault_access_o || fault_code_o !== expected_code ||
natv_nmi.valid || apb_nmi.valid) begin
rib.valid || apb_rib.valid) begin
$fatal(1, "unexpected fault response for address %h", address);
end
while (!mgmt_nmi.ready) @(posedge clk_i);
if (mgmt_nmi.rdata !== 32'd0 || !mgmt_nmi.resp_err ||
mgmt_nmi.resp_code !== expected_code) begin
while (!mgmt_rib.ready) @(posedge clk_i);
if (mgmt_rib.rdata !== 32'd0 || !mgmt_rib.resp_err ||
mgmt_rib.resp_code !== expected_code) begin
$fatal(1, "fault response data must be zero");
end
@(negedge clk_i);
mgmt_nmi.valid = 1'b0;
mgmt_rib.valid = 1'b0;
while (fault_valid_o) @(posedge clk_i);
end
endtask
@@ -74,44 +74,44 @@ module bus_fault_tb;
task automatic expect_user_denied(input logic [31:0] address, input logic [3:0] write_strobes);
begin
@(negedge clk_i);
user_nmi.addr = address;
user_nmi.wdata = 32'h5A5A_A5A5;
user_nmi.wstrb = write_strobes;
user_nmi.valid = 1'b1;
user_rib.addr = address;
user_rib.wdata = 32'h5A5A_A5A5;
user_rib.wstrb = write_strobes;
user_rib.valid = 1'b1;
while (!fault_valid_o) @(posedge clk_i);
if (!fault_access_o || fault_master_o != 2'd1 || natv_nmi.valid || apb_nmi.valid) begin
if (!fault_access_o || fault_master_o != 2'd1 || rib.valid || apb_rib.valid) begin
$fatal(1, "user access was not denied locally");
end
while (!user_nmi.ready) @(posedge clk_i);
if (user_nmi.rdata !== 32'd0 || !user_nmi.resp_err ||
user_nmi.resp_code !== `SOC_NMI_RESP_PROTERR) begin
while (!user_rib.ready) @(posedge clk_i);
if (user_rib.rdata !== 32'd0 || !user_rib.resp_err ||
user_rib.resp_code !== `SOC_RIB_RESP_PROTERR) begin
$fatal(1, "denied user response data must be zero");
end
@(negedge clk_i);
user_nmi.valid = 1'b0;
user_rib.valid = 1'b0;
while (fault_valid_o) @(posedge clk_i);
end
endtask
initial begin
mgmt_nmi.valid = 1'b0;
mgmt_nmi.addr = '0;
mgmt_nmi.wdata = '0;
mgmt_nmi.wstrb = '0;
user_nmi.valid = 1'b0;
user_nmi.addr = '0;
user_nmi.wdata = '0;
user_nmi.wstrb = '0;
dma_nmi.valid = 1'b0;
dma_nmi.addr = '0;
dma_nmi.wdata = '0;
dma_nmi.wstrb = '0;
mgmt_rib.valid = 1'b0;
mgmt_rib.addr = '0;
mgmt_rib.wdata = '0;
mgmt_rib.wstrb = '0;
user_rib.valid = 1'b0;
user_rib.addr = '0;
user_rib.wdata = '0;
user_rib.wstrb = '0;
dma_rib.valid = 1'b0;
dma_rib.addr = '0;
dma_rib.wdata = '0;
dma_rib.wstrb = '0;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_fault(32'h1000_F000, 4'hF, 1'b1, `SOC_NMI_RESP_RESERVED);
expect_fault(32'hA000_0000, 4'h0, 1'b0, `SOC_NMI_RESP_DECERR);
expect_fault(32'h1000_F000, 4'hF, 1'b1, `SOC_RIB_RESP_RESERVED);
expect_fault(32'hA000_0000, 4'h0, 1'b0, `SOC_RIB_RESP_DECERR);
expect_user_denied(32'h1000_B000, 4'hF);
$display("bus fault responder test passed");
$finish;
tests/rtl/dma_error_tb.sv
+8 -8
View File
@@ -20,17 +20,17 @@ module dma_error_tb;
logic error_mode = 1'b0;
integer write_count = 0;
dma_hw_trg_if hw_trg ();
soc_nmi_if nmi ();
soc_rib_if rib ();
always #5 clk_i = ~clk_i;
assign nmi.ready = nmi.valid;
assign nmi.rdata = 32'hA5A5_5A5A;
assign nmi.resp_err = error_mode && nmi.valid;
assign nmi.resp_code = error_mode ? `SOC_NMI_RESP_DECERR : `SOC_NMI_RESP_OK;
assign rib.ready = rib.valid;
assign rib.rdata = 32'hA5A5_5A5A;
assign rib.resp_err = error_mode && rib.valid;
assign rib.resp_code = error_mode ? `SOC_RIB_RESP_DECERR : `SOC_RIB_RESP_OK;
always @(posedge clk_i) begin
if (nmi.valid && nmi.ready && (|nmi.wstrb)) begin
if (rib.valid && rib.ready && (|rib.wstrb)) begin
write_count <= write_count + 1;
end
end
@@ -53,7 +53,7 @@ module dma_error_tb;
.error_addr_o(error_addr_o),
.fsm_o (fsm_o),
.hw_trg (hw_trg),
.nmi (nmi)
.rib (rib)
);
task automatic start_transfer;
@@ -84,7 +84,7 @@ module dma_error_tb;
start_transfer();
wait (error_o);
@(negedge clk_i);
if (error_code_o !== `SOC_NMI_RESP_DECERR || error_addr_o !== srcaddr_i) begin
if (error_code_o !== `SOC_RIB_RESP_DECERR || error_addr_o !== srcaddr_i) begin
$fatal(1, "DMA error response was not propagated");
end
if (write_count != 1) begin
tests/rtl/gpio_user_mux_tb.sv
+25 -25
View File
@@ -3,17 +3,17 @@
module gpio_user_mux_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
nmi_if nmi ();
rib_if rib ();
gpio_if gpio ();
user_gpio_if user_gpio ();
logic [31:0] read_data;
always #5 clk_i = ~clk_i;
nmi_gpio dut (
rib_gpio dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.nmi (nmi),
.rib (rib),
.gpio (gpio),
.user_gpio(user_gpio)
);
@@ -21,14 +21,14 @@ module gpio_user_mux_tb;
task automatic write_register(input logic [7:0] address, input logic [31:0] data);
begin
@(negedge clk_i);
nmi.addr = {24'd0, address};
nmi.wdata = data;
nmi.wstrb = 4'hF;
nmi.valid = 1'b1;
rib.addr = {24'd0, address};
rib.wdata = data;
rib.wstrb = 4'hF;
rib.valid = 1'b1;
@(posedge clk_i);
#1;
@(negedge clk_i);
nmi.valid = 1'b0;
rib.valid = 1'b0;
@(posedge clk_i);
#1;
end
@@ -37,15 +37,15 @@ module gpio_user_mux_tb;
task automatic read_register(input logic [7:0] address, output logic [31:0] data);
begin
@(negedge clk_i);
nmi.addr = {24'd0, address};
nmi.wdata = '0;
nmi.wstrb = '0;
nmi.valid = 1'b1;
rib.addr = {24'd0, address};
rib.wdata = '0;
rib.wstrb = '0;
rib.valid = 1'b1;
@(posedge clk_i);
#1;
data = nmi.rdata;
data = rib.rdata;
@(negedge clk_i);
nmi.valid = 1'b0;
rib.valid = 1'b0;
@(posedge clk_i);
#1;
end
@@ -54,25 +54,25 @@ module gpio_user_mux_tb;
task automatic select_user_gpio(input logic [31:0] selection);
begin
@(negedge clk_i);
nmi.addr = 32'h0000_0030;
nmi.wdata = selection;
nmi.wstrb = 4'hF;
nmi.valid = 1'b1;
rib.addr = 32'h0000_0030;
rib.wdata = selection;
rib.wstrb = 4'hF;
rib.valid = 1'b1;
@(posedge clk_i);
#1;
if (gpio.oe_o[0] !== 1'b0) $fatal(1, "GPIO handoff did not drive high impedance");
@(negedge clk_i);
nmi.valid = 1'b0;
rib.valid = 1'b0;
@(posedge clk_i);
#1;
end
endtask
initial begin
nmi.valid = 1'b0;
nmi.addr = '0;
nmi.wdata = '0;
nmi.wstrb = '0;
rib.valid = 1'b0;
rib.addr = '0;
rib.wdata = '0;
rib.wstrb = '0;
gpio.di_i = '0;
gpio.alt0_do_i = '0;
gpio.alt0_oe_i = '0;
@@ -87,7 +87,7 @@ module gpio_user_mux_tb;
write_register(8'h00, 32'h0000_0001);
write_register(8'h10, 32'h0000_0001);
if ({gpio.oe_o[0], gpio.do_o[0]} !== 2'b11) $fatal(1, "native software GPIO is not active");
if ({gpio.oe_o[0], gpio.do_o[0]} !== 2'b11) $fatal(1, "rib software GPIO is not active");
user_gpio.do_o[0] = 1'b0;
user_gpio.oe_o[0] = 1'b1;
@@ -119,7 +119,7 @@ module gpio_user_mux_tb;
write_register(8'h08, 32'h0000_0001);
write_register(8'h0C, 32'h0000_0001);
if ({gpio.cs_o[0], gpio.pu_o[0], gpio.pd_o[0]} !== 3'b111)
$fatal(1, "native GPIO electrical controls changed under user ownership");
$fatal(1, "rib GPIO electrical controls changed under user ownership");
$display("GPIO user ownership test passed");
$finish;
tests/rtl/pll_ctrl_tb.sv
+22 -22
View File
@@ -9,7 +9,7 @@ module pll_ctrl_tb;
logic [31:0] fault_addr_i = '0;
logic [ 3:0] fault_wstrb_i = '0;
logic fault_reserved_i = 1'b0;
nmi_if nmi ();
rib_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
logic sys_clk_o;
@@ -38,14 +38,14 @@ module pll_ctrl_tb;
.sys_clkdiv4_o(sys_clkdiv4_o)
);
nmi_sysctrl u_sysctrl (
rib_sysctrl u_sysctrl (
.clk_i (sys_clk_o),
.rst_n_i (sys_rst_n_o),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.nmi (nmi),
.rib (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
@@ -53,29 +53,29 @@ module pll_ctrl_tb;
task automatic read_register(input logic [31:0] address, output logic [31:0] data);
begin
@(negedge sys_clk_o);
nmi.addr = address;
nmi.wdata = '0;
nmi.wstrb = '0;
nmi.valid = 1'b1;
while (!nmi.ready) @(posedge sys_clk_o);
data = nmi.rdata;
rib.addr = address;
rib.wdata = '0;
rib.wstrb = '0;
rib.valid = 1'b1;
while (!rib.ready) @(posedge sys_clk_o);
data = rib.rdata;
@(negedge sys_clk_o);
nmi.valid = 1'b0;
while (nmi.ready) @(posedge sys_clk_o);
rib.valid = 1'b0;
while (rib.ready) @(posedge sys_clk_o);
end
endtask
task automatic write_register(input logic [31:0] address, input logic [31:0] data);
begin
@(negedge sys_clk_o);
nmi.addr = address;
nmi.wdata = data;
nmi.wstrb = 4'hF;
nmi.valid = 1'b1;
while (!nmi.ready) @(posedge sys_clk_o);
rib.addr = address;
rib.wdata = data;
rib.wstrb = 4'hF;
rib.valid = 1'b1;
while (!rib.ready) @(posedge sys_clk_o);
@(negedge sys_clk_o);
nmi.valid = 1'b0;
while (nmi.ready) @(posedge sys_clk_o);
rib.valid = 1'b0;
while (rib.ready) @(posedge sys_clk_o);
end
endtask
@@ -98,10 +98,10 @@ module pll_ctrl_tb;
endtask
initial begin
nmi.valid = 1'b0;
nmi.addr = '0;
nmi.wdata = '0;
nmi.wstrb = '0;
rib.valid = 1'b0;
rib.addr = '0;
rib.wdata = '0;
rib.wstrb = '0;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
tests/rtl/sdram_data_tb.sv
+21 -21
View File
@@ -5,7 +5,7 @@ module sdram_data_tb;
logic rst_n_i = 1'b0;
wire [15:0] s_dq;
logic [31:0] s_read_data;
nmi_if nmi ();
rib_if rib ();
sdram_if sdram ();
always #5 clk_i = ~clk_i;
@@ -13,10 +13,10 @@ module sdram_data_tb;
assign s_dq = sdram.oe_o ? sdram.dq_o : 'z;
assign sdram.dq_i = s_dq;
nmi_sdram u_nmi_sdram (
rib_sdram u_rib_sdram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.nmi (nmi),
.rib (rib),
.sdram (sdram)
);
@@ -52,40 +52,40 @@ module sdram_data_tb;
input logic [3:0] strobe);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.wdata = data;
nmi.wstrb = strobe;
nmi.valid = 1'b1;
rib.addr = address;
rib.wdata = data;
rib.wstrb = strobe;
rib.valid = 1'b1;
do begin
@(posedge clk_i);
end while (!nmi.ready);
end while (!rib.ready);
@(negedge clk_i);
nmi.valid = 1'b0;
nmi.wstrb = '0;
rib.valid = 1'b0;
rib.wstrb = '0;
end
endtask
task automatic read_word(input logic [31:0] address);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.wdata = '0;
nmi.wstrb = '0;
nmi.valid = 1'b1;
rib.addr = address;
rib.wdata = '0;
rib.wstrb = '0;
rib.valid = 1'b1;
do begin
@(posedge clk_i);
end while (!nmi.ready);
s_read_data = nmi.rdata;
end while (!rib.ready);
s_read_data = rib.rdata;
@(negedge clk_i);
nmi.valid = 1'b0;
rib.valid = 1'b0;
end
endtask
initial begin
nmi.addr = '0;
nmi.valid = 1'b0;
nmi.wdata = '0;
nmi.wstrb = '0;
rib.addr = '0;
rib.valid = 1'b0;
rib.wdata = '0;
rib.wstrb = '0;
repeat (4) @(posedge clk_i);
rst_n_i = 1'b1;
tests/rtl/soc_irq_topology_tb.sv
+6 -6
View File
@@ -4,7 +4,7 @@
module soc_irq_topology_tb;
logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
logic [ `SOC_IRQ_NMI_WIDTH-1:0] s_nmi_irq;
logic [ `SOC_IRQ_RIB_WIDTH-1:0] s_rib_irq;
logic [ `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
`include "soc_irq_wiring.svh"
@@ -19,19 +19,19 @@ module soc_irq_topology_tb;
endtask
initial begin
s_nmi_irq = '0;
s_rib_irq = '0;
s_apb_irq = '0;
expect_irq('0);
for (int bit_index = 0; bit_index < `SOC_IRQ_NMI_WIDTH; bit_index++) begin
s_nmi_irq = '0;
s_nmi_irq[bit_index] = 1'b1;
for (int bit_index = 0; bit_index < `SOC_IRQ_RIB_WIDTH; bit_index++) begin
s_rib_irq = '0;
s_rib_irq[bit_index] = 1'b1;
s_apb_irq = '0;
expect_irq(32'd1 << bit_index);
end
for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
s_nmi_irq = '0;
s_rib_irq = '0;
s_apb_irq = '0;
s_apb_irq[bit_index] = 1'b1;
expect_irq(32'd1 << (10 + bit_index));
tests/rtl/soc_topology_nmi_tb.sv
-112
View File
@@ -1,112 +0,0 @@
`timescale 1ns / 1ps
`include "mmap_define.svh"
module soc_topology_nmi_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
nmi_if nmi ();
`include "soc_nmi_interfaces.svh"
`include "soc_nmi_routes.svh"
always #5 clk_i = ~clk_i;
task automatic expect_route(input logic [31:0] address, input integer slot,
input logic [31:0] expected_rdata);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.valid = 1'b1;
#1;
if (s_slv_sel_d !== (18'd1 << slot)) begin
$fatal(1, "unexpected target slot for %h", address);
end
@(posedge clk_i);
#1;
if (!nmi.ready || nmi.rdata !== expected_rdata) begin
$fatal(1, "unexpected response for %h", address);
end
@(negedge clk_i);
nmi.valid = 1'b0;
@(posedge clk_i);
end
endtask
task automatic expect_disabled(input logic [31:0] address);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.valid = 1'b1;
#1;
if (s_slv_sel_d !== '0) begin
$fatal(1, "disabled target accepted %h", address);
end
@(posedge clk_i);
#1;
if (nmi.ready || nmi.rdata !== '0) begin
$fatal(1, "disabled target responded to %h", address);
end
@(negedge clk_i);
nmi.valid = 1'b0;
@(posedge clk_i);
end
endtask
initial begin
nmi.valid = 1'b0;
nmi.addr = '0;
nmi.wdata = '0;
nmi.wstrb = '0;
u_uart_nmi_if.ready = 1'b1;
u_gpio_nmi_if.ready = 1'b1;
u_tim0_nmi_if.ready = 1'b1;
u_tim1_nmi_if.ready = 1'b1;
u_psram_nmi_if.ready = 1'b1;
u_spisd_nmi_if.ready = 1'b1;
u_i2c0_nmi_if.ready = 1'b1;
u_i2s_nmi_if.ready = 1'b1;
u_onewire_nmi_if.ready = 1'b1;
u_xpi_nmi_if.ready = 1'b1;
u_dma_nmi_if.ready = 1'b1;
u_sysctrl_nmi_if.ready = 1'b1;
u_clint_nmi_if.ready = 1'b1;
u_sdram_nmi_if.ready = 1'b1;
u_dvp_nmi_if.ready = 1'b1;
u_sdio_nmi_if.ready = 1'b1;
u_opipsram_nmi_if.ready = 1'b1;
u_i2c1_nmi_if.ready = 1'b1;
u_uart_nmi_if.rdata = 32'h0000_0000;
u_gpio_nmi_if.rdata = 32'h1111_1111;
u_tim0_nmi_if.rdata = 32'h2222_2222;
u_tim1_nmi_if.rdata = 32'h3333_3333;
u_psram_nmi_if.rdata = 32'h4444_4444;
u_spisd_nmi_if.rdata = 32'h5555_5555;
u_i2c0_nmi_if.rdata = 32'h6666_6666;
u_i2s_nmi_if.rdata = 32'h7777_7777;
u_onewire_nmi_if.rdata = 32'h8888_8888;
u_xpi_nmi_if.rdata = 32'h9999_9999;
u_dma_nmi_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_nmi_if.rdata = 32'hBBBB_BBBB;
u_clint_nmi_if.rdata = 32'hCCCC_CCCC;
u_sdram_nmi_if.rdata = 32'hDDDD_DDDD;
u_dvp_nmi_if.rdata = 32'hEEEE_EEEE;
u_sdio_nmi_if.rdata = 32'hF0F0_F0F0;
u_opipsram_nmi_if.rdata = 32'h0F0F_0F0F;
u_i2c1_nmi_if.rdata = 32'h1234_5678;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_route(`SOC_ADDR_NMI_GPIO_BASE, 1, 32'h1111_1111);
expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
expect_route(`SOC_ADDR_NMI_I2C1_BASE, 17, 32'h1234_5678);
expect_disabled(`SOC_ADDR_NMI_SDIO_BASE);
$display("SoC topology NMI routing test passed");
$finish;
end
endmodule
tests/rtl/soc_topology_rib_tb.sv
+112
View File
@@ -0,0 +1,112 @@
`timescale 1ns / 1ps
`include "mmap_define.svh"
module soc_topology_rib_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
rib_if rib ();
`include "soc_rib_interfaces.svh"
`include "soc_rib_routes.svh"
always #5 clk_i = ~clk_i;
task automatic expect_route(input logic [31:0] address, input integer slot,
input logic [31:0] expected_rdata);
begin
@(negedge clk_i);
rib.addr = address;
rib.valid = 1'b1;
#1;
if (s_slv_sel_d !== (18'd1 << slot)) begin
$fatal(1, "unexpected target slot for %h", address);
end
@(posedge clk_i);
#1;
if (!rib.ready || rib.rdata !== expected_rdata) begin
$fatal(1, "unexpected response for %h", address);
end
@(negedge clk_i);
rib.valid = 1'b0;
@(posedge clk_i);
end
endtask
task automatic expect_disabled(input logic [31:0] address);
begin
@(negedge clk_i);
rib.addr = address;
rib.valid = 1'b1;
#1;
if (s_slv_sel_d !== '0) begin
$fatal(1, "disabled target accepted %h", address);
end
@(posedge clk_i);
#1;
if (rib.ready || rib.rdata !== '0) begin
$fatal(1, "disabled target responded to %h", address);
end
@(negedge clk_i);
rib.valid = 1'b0;
@(posedge clk_i);
end
endtask
initial begin
rib.valid = 1'b0;
rib.addr = '0;
rib.wdata = '0;
rib.wstrb = '0;
u_uart_rib_if.ready = 1'b1;
u_gpio_rib_if.ready = 1'b1;
u_tim0_rib_if.ready = 1'b1;
u_tim1_rib_if.ready = 1'b1;
u_psram_rib_if.ready = 1'b1;
u_spisd_rib_if.ready = 1'b1;
u_i2c0_rib_if.ready = 1'b1;
u_i2s_rib_if.ready = 1'b1;
u_onewire_rib_if.ready = 1'b1;
u_xpi_rib_if.ready = 1'b1;
u_dma_rib_if.ready = 1'b1;
u_sysctrl_rib_if.ready = 1'b1;
u_clint_rib_if.ready = 1'b1;
u_sdram_rib_if.ready = 1'b1;
u_dvp_rib_if.ready = 1'b1;
u_sdio_rib_if.ready = 1'b1;
u_opipsram_rib_if.ready = 1'b1;
u_i2c1_rib_if.ready = 1'b1;
u_uart_rib_if.rdata = 32'h0000_0000;
u_gpio_rib_if.rdata = 32'h1111_1111;
u_tim0_rib_if.rdata = 32'h2222_2222;
u_tim1_rib_if.rdata = 32'h3333_3333;
u_psram_rib_if.rdata = 32'h4444_4444;
u_spisd_rib_if.rdata = 32'h5555_5555;
u_i2c0_rib_if.rdata = 32'h6666_6666;
u_i2s_rib_if.rdata = 32'h7777_7777;
u_onewire_rib_if.rdata = 32'h8888_8888;
u_xpi_rib_if.rdata = 32'h9999_9999;
u_dma_rib_if.rdata = 32'hAAAA_AAAA;
u_sysctrl_rib_if.rdata = 32'hBBBB_BBBB;
u_clint_rib_if.rdata = 32'hCCCC_CCCC;
u_sdram_rib_if.rdata = 32'hDDDD_DDDD;
u_dvp_rib_if.rdata = 32'hEEEE_EEEE;
u_sdio_rib_if.rdata = 32'hF0F0_F0F0;
u_opipsram_rib_if.rdata = 32'h0F0F_0F0F;
u_i2c1_rib_if.rdata = 32'h1234_5678;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_route(`SOC_ADDR_RIB_GPIO_BASE, 1, 32'h1111_1111);
expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
expect_route(`SOC_ADDR_RIB_I2C1_BASE, 17, 32'h1234_5678);
expect_disabled(`SOC_ADDR_RIB_SDIO_BASE);
$display("SoC topology RIB routing test passed");
$finish;
end
endmodule
tests/rtl/sysctrl_fault_tb.sv
+27 -27
View File
@@ -7,20 +7,20 @@ module sysctrl_fault_tb;
logic [31:0] fault_addr_i = '0;
logic [ 3:0] fault_wstrb_i = '0;
logic fault_reserved_i = 1'b0;
nmi_if nmi ();
rib_if rib ();
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
always #5 clk_i = ~clk_i;
nmi_sysctrl u_sysctrl (
rib_sysctrl u_sysctrl (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.nmi (nmi),
.rib (rib),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
);
@@ -28,46 +28,46 @@ module sysctrl_fault_tb;
task automatic read_register(input logic [31:0] address, output logic [31:0] data);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.wdata = '0;
nmi.wstrb = '0;
nmi.valid = 1'b1;
while (!nmi.ready) @(posedge clk_i);
data = nmi.rdata;
rib.addr = address;
rib.wdata = '0;
rib.wstrb = '0;
rib.valid = 1'b1;
while (!rib.ready) @(posedge clk_i);
data = rib.rdata;
@(negedge clk_i);
nmi.valid = 1'b0;
while (nmi.ready) @(posedge clk_i);
rib.valid = 1'b0;
while (rib.ready) @(posedge clk_i);
end
endtask
task automatic write_register(input logic [31:0] address, input logic [31:0] data);
begin
@(negedge clk_i);
nmi.addr = address;
nmi.wdata = data;
nmi.wstrb = 4'hF;
nmi.valid = 1'b1;
while (!nmi.ready) @(posedge clk_i);
rib.addr = address;
rib.wdata = data;
rib.wstrb = 4'hF;
rib.valid = 1'b1;
while (!rib.ready) @(posedge clk_i);
@(negedge clk_i);
nmi.valid = 1'b0;
while (nmi.ready) @(posedge clk_i);
rib.valid = 1'b0;
while (rib.ready) @(posedge clk_i);
end
endtask
logic [31:0] read_data;
initial begin
nmi.valid = 1'b0;
nmi.addr = '0;
nmi.wdata = '0;
nmi.wstrb = '0;
rib.valid = 1'b0;
rib.addr = '0;
rib.wdata = '0;
rib.wstrb = '0;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
sysctrl.fault_code_i = `SOC_NMI_RESP_RESERVED;
sysctrl.fault_code_i = `SOC_RIB_RESP_RESERVED;
sysctrl.perf_mgmt_wait_i = 64'd11;
sysctrl.perf_user_wait_i = 64'd12;
sysctrl.perf_dma_wait_i = 64'd13;
sysctrl.perf_natv_wait_i = 64'd14;
sysctrl.perf_rib_wait_i = 64'd14;
sysctrl.perf_apb_wait_i = 64'd15;
sysctrl.perf_sdram_wait_i = 64'd16;
sysctrl.perf_psram_wait_i = 64'd17;
@@ -98,10 +98,10 @@ module sysctrl_fault_tb;
read_register(32'h1000_B018, read_data);
if (read_data !== 32'h0000_0001) $fatal(1, "fault count was not incremented");
read_register(32'h1000_B02C, read_data);
if (read_data !== `SOC_NMI_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
@(negedge clk_i);
sysctrl.fault_code_i = `SOC_NMI_RESP_DECERR;
sysctrl.fault_code_i = `SOC_RIB_RESP_DECERR;
fault_valid_i = 1'b1;
fault_addr_i = 32'hA000_0000;
fault_wstrb_i = 4'h0;
@@ -113,7 +113,7 @@ module sysctrl_fault_tb;
read_register(32'h1000_B018, read_data);
if (read_data !== 32'h0000_0002) $fatal(1, "later fault did not increment count");
read_register(32'h1000_B02C, read_data);
if (read_data !== `SOC_NMI_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
write_register(32'h1000_B010, 32'h0000_0001);
read_register(32'h1000_B010, read_data);
tests/test_dma.py
+4 -4
View File
@@ -24,11 +24,11 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
"+define+SV_ASSRT_DISABLE",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/mini/top/soc_nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/native/peripheral/dma.sv"),
str(ROOT / "rtl/ip/native/peripheral/dma_core.sv"),
str(ROOT / "rtl/ip/rib/peripheral/dma.sv"),
str(ROOT / "rtl/ip/rib/peripheral/dma_core.sv"),
str(ROOT / "tests/rtl/dma_error_tb.sv"),
"",
]
tests/test_gpio_user_mux.py
+5 -5
View File
@@ -1,4 +1,4 @@
"""RTL tests for user-IP ownership of the native GPIO pad bank."""
"""RTL tests for user-IP ownership of the rib GPIO pad bank."""
from __future__ import annotations
@@ -11,7 +11,7 @@ from pathlib import Path
ROOT = Path(__file__).resolve().parents[1]
def test_user_ip_can_own_native_gpio_pads_with_a_safe_handoff(tmp_path: Path) -> None:
def test_user_ip_can_own_rib_gpio_pads_with_a_safe_handoff(tmp_path: Path) -> None:
iverilog = shutil.which("iverilog")
sv2v = shutil.which("sv2v")
vvp = shutil.which("vvp")
@@ -23,13 +23,13 @@ def test_user_ip_can_own_native_gpio_pads_with_a_safe_handoff(tmp_path: Path) ->
"\n".join(
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{ROOT / 'rtl/ip/native/peripheral'}",
f"+incdir+{ROOT / 'rtl/ip/rib/peripheral'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
str(ROOT / "rtl/ip/native/peripheral/gpio.sv"),
str(ROOT / "rtl/ip/rib/peripheral/gpio.sv"),
str(ROOT / "tests/rtl/gpio_user_mux_tb.sv"),
"",
]
tests/test_memory_map.py
+18 -15
View File
@@ -58,11 +58,14 @@ def test_generated_artifacts_share_the_capacity_baseline(tmp_path: Path) -> None
assert "RS_SOC_PSRAM_SIZE UINT32_C(0x00800000)" in header
assert "RS_SOC_SDRAM_SIZE UINT32_C(0x02000000)" in header
assert "RS_SOC_SPISD_SIZE UINT32_C(0x40000000)" in header
assert "RS_SOC_NMI_SDIO_BASE" not in header
assert "RS_SOC_RIB_SDIO_BASE" not in header
assert "RS_SOC_NMI_" not in header
assert "RS_SOC_OPIPSRAM_BASE" not in header
assert "RS_SOC_HAS_SRAM 1U" in header
assert "SOC_SYSCTRL_PLL_CFG_OFFSET 32'h00000008" in rtl
assert "SOC_SYSCTRL_PLL_STATUS_OFFSET 32'h0000001C" in rtl
assert "SOC_ADDR_IS_RIB(addr)" in rtl
assert "SOC_ADDR_IS_NMI" not in rtl
assert "RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)" in header
assert "RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)" in header
assert "PSRAM (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 0x00800000" in linker
@@ -109,10 +112,10 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P
f"+incdir+{tmp_path / 'rtl'}",
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/mini/top/soc_nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/mini/top/soc_nmi_regslice.sv"),
str(ROOT / "rtl/mini/top/soc_rib_regslice.sv"),
str(ROOT / "rtl/mini/top/bus.sv"),
str(ROOT / "tests/rtl/bus_fault_tb.sv"),
"",
@@ -163,11 +166,11 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/mini/top/soc_nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/native/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/native/peripheral/sysctrl.sv"),
str(ROOT / "rtl/ip/rib/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/rib/peripheral/sysctrl.sv"),
str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"),
"",
]
@@ -212,14 +215,14 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
f"+incdir+{tmp_path / 'user_extensions' / 'rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/mini/top/soc_nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"),
str(ROOT / "rtl/ip/native/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/native/peripheral/sysctrl.sv"),
str(ROOT / "rtl/ip/rib/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/rib/peripheral/sysctrl.sv"),
str(ROOT / "rtl/tech/tc_clk.sv"),
str(ROOT / "rtl/tech/tc_pll.sv"),
str(ROOT / "rtl/mini/top/rcu.sv"),
@@ -290,12 +293,12 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
rtl = (ROOT / "rtl/ip/native/peripheral/sysctrl.sv").read_text(encoding="utf-8")
rtl = (ROOT / "rtl/ip/rib/peripheral/sysctrl.sv").read_text(encoding="utf-8")
header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
for symbol in (
"NATV_SYSCTRL_I2CSEL",
"NATV_SYSCTRL_QSPISEL",
"RIB_SYSCTRL_I2CSEL",
"RIB_SYSCTRL_QSPISEL",
"i2c_sel_o",
"qspi_sel_o",
"s_sysctrl_i2csel",
tests/test_performance_log.py
+4 -4
View File
@@ -8,7 +8,7 @@ from scripts.parse_performance_log import parse_log
def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 mgmt_wait=10 "
"native_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_BENCHMARK_PASS\n"
)
@@ -21,7 +21,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
"dma_wait": 0,
"flash_wait": 0,
"mgmt_wait": 10,
"native_wait": 9,
"rib_wait": 9,
"operation": "read",
"psram_wait": 0,
"region": "sdram",
@@ -33,7 +33,7 @@ def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
def test_parse_log_rejects_missing_benchmark_marker() -> None:
report = parse_log(
"PERF region=flash op=read words=1024 checksum=0 mgmt_wait=1 native_wait=1 "
"PERF region=flash op=read words=1024 checksum=0 mgmt_wait=1 rib_wait=1 "
"sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
)
@@ -43,7 +43,7 @@ def test_parse_log_rejects_missing_benchmark_marker() -> None:
def test_parse_log_rejects_report_with_performance_failure() -> None:
report = parse_log(
"PERF region=sdram op=read words=1024 checksum=0x1234 mgmt_wait=10 "
"native_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
"PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
"PERF_BENCHMARK_PASS\n"
)
tests/test_script_tools.py
+14 -14
View File
@@ -179,13 +179,13 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
(user_extensions / "rtl").mkdir(parents=True)
bus_filelist = tmp_path / "bus.fl"
nmi2apb_filelist = tmp_path / "nmi2apb.fl"
rib2apb_filelist = tmp_path / "rib2apb.fl"
sysctrl_filelist = tmp_path / "sysctrl.fl"
pll_rcu_filelist = tmp_path / "pll_rcu.fl"
gpio_user_filelist = tmp_path / "gpio_user.fl"
assert generate_formal_filelist("bus", bus_filelist, memory_map, topology, user_extensions)
assert generate_formal_filelist(
"nmi2apb", nmi2apb_filelist, memory_map, topology, user_extensions
"rib2apb", rib2apb_filelist, memory_map, topology, user_extensions
)
assert generate_formal_filelist(
"sysctrl", sysctrl_filelist, memory_map, topology, user_extensions
@@ -198,22 +198,22 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
)
bus = parse_filelists([bus_filelist], require_files=False)
nmi2apb = parse_filelists([nmi2apb_filelist], require_files=False)
rib2apb = parse_filelists([rib2apb_filelist], require_files=False)
sysctrl = parse_filelists([sysctrl_filelist], require_files=False)
pll_rcu = parse_filelists([pll_rcu_filelist], require_files=False)
gpio_user = parse_filelists([gpio_user_filelist], require_files=False)
assert "+define+SV_ASSRT_DISABLE" in bus.defines
assert ROOT / "rtl/mini/top/bus.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_nmi_regslice.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_regslice.sv" in bus.files
assert ROOT / "rtl/mini/formal/bus_formal.sv" in bus.files
assert ROOT / "rtl/ip/native/interconnect/nmi2apb.sv" in nmi2apb.files
assert ROOT / "rtl/mini/formal/nmi2apb_formal.sv" in nmi2apb.files
assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in nmi2apb.files
assert ROOT / "rtl/ip/native/peripheral/sysctrl.sv" in sysctrl.files
assert ROOT / "rtl/ip/rib/interconnect/rib2apb.sv" in rib2apb.files
assert ROOT / "rtl/mini/formal/rib2apb_formal.sv" in rib2apb.files
assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in rib2apb.files
assert ROOT / "rtl/ip/rib/peripheral/sysctrl.sv" in sysctrl.files
assert ROOT / "rtl/mini/formal/sysctrl_formal.sv" in sysctrl.files
assert ROOT / "rtl/mini/top/rcu.sv" in pll_rcu.files
assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv" in pll_rcu.files
assert ROOT / "rtl/ip/native/peripheral/gpio.sv" in gpio_user.files
assert ROOT / "rtl/ip/rib/peripheral/gpio.sv" in gpio_user.files
assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in gpio_user.files
assert ROOT / "rtl/mini/formal/gpio_user_formal.sv" in gpio_user.files
@@ -248,7 +248,7 @@ def test_fatfs_release_script_uses_the_locked_archive_contract() -> None:
def test_formal_result_summary_requires_every_passing_step(tmp_path: Path) -> None:
proofs = ("bus", "nmi2apb", "sysctrl", "pll_rcu", "gpio_user")
proofs = ("bus", "rib2apb", "sysctrl", "pll_rcu", "gpio_user")
for proof in proofs:
directory = tmp_path / proof
directory.mkdir()
@@ -270,7 +270,7 @@ def test_formal_result_summary_requires_every_passing_step(tmp_path: Path) -> No
"--proof",
f"bus={tmp_path / 'bus'}",
"--proof",
f"nmi2apb={tmp_path / 'nmi2apb'}",
f"rib2apb={tmp_path / 'rib2apb'}",
"--proof",
f"sysctrl={tmp_path / 'sysctrl'}",
"--proof",
@@ -504,7 +504,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
Path("Makefile"),
Path("configs/ci/example.mk"),
Path("rtl/mini/top/retrosoc.sv"),
Path("rtl/ip/native/peripheral/sysctrl.sv"),
Path("rtl/ip/rib/peripheral/sysctrl.sv"),
Path("rtl/tech/tc_clk.sv"),
Path("rtl/demo/reference.v"),
Path("rtl/managed/clusterip/common/rtl/utils/register.sv"),
@@ -518,7 +518,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None:
]
assert format_files(paths, "rtl") == [
Path("rtl/demo/reference.v"),
Path("rtl/ip/native/peripheral/sysctrl.sv"),
Path("rtl/ip/rib/peripheral/sysctrl.sv"),
Path("rtl/mini/top/retrosoc.sv"),
Path("rtl/tech/tc_clk.sv"),
]
@@ -620,7 +620,7 @@ def test_management_core_selection_is_limited_to_hazard3_and_picorv32() -> None:
assert "DEF_LIST += +define+CORE_$(CORE)" in makefile
assert "`ifdef CORE_PICORV32" in wrapper
assert "`elsif CORE_HAZARD3" in wrapper
assert "ahbl2soc_nmi u_ahbl2soc_nmi" in wrapper
assert "ahbl2soc_rib u_ahbl2soc_rib" in wrapper
assert ".RESET_VECTOR (`SOC_CPU_RESET_ADDR)" in wrapper
tests/test_sdram.py
+10 -10
View File
@@ -36,12 +36,12 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/native/memory/sdram.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "rtl/mini/dv/verilator/rtl/sdram_verilator_model.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
@@ -97,12 +97,12 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/native/memory/sdram.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/native/memory/sdram_core.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_reg.sv"),
str(ROOT / "rtl/ip/rib/memory/sdram_core.sv"),
str(ROOT / "tests/rtl/sdram_data_tb.sv"),
"",
]
tests/test_soc_topology.py
+47 -44
View File
@@ -54,11 +54,11 @@ def write_invalid_topology(tmp_path: Path, document: dict[str, object]) -> Path:
return path
def test_topology_generates_complete_native_apb_and_gpio_bindings(tmp_path: Path) -> None:
def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -> None:
generate(tmp_path)
interfaces = (tmp_path / "rtl/soc_nmi_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/soc_nmi_routes.svh").read_text(encoding="utf-8")
interfaces = (tmp_path / "rtl/soc_rib_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/soc_rib_routes.svh").read_text(encoding="utf-8")
gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
@@ -67,32 +67,35 @@ def test_topology_generates_complete_native_apb_and_gpio_bindings(tmp_path: Path
fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
nmi_irq = (tmp_path / "rtl/soc_nmi_irq_bindings.svh").read_text(encoding="utf-8")
rib_irq = (tmp_path / "rtl/soc_rib_irq_bindings.svh").read_text(encoding="utf-8")
apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
filelist = (tmp_path / "soc_topology.fl").read_text(encoding="utf-8")
assert interfaces.count("nmi_if u_") == 18
assert "assign s_slv_sel_d[17] = u_i2c1_nmi_if.valid;" in routes
assert "assign s_xpi_region_sel[1] = (nmi.addr <= `SOC_ADDR_FLASH_END);" in routes
assert "assign u_sdio_nmi_if.valid = 1'b0;" in routes
assert interfaces.count("rib_if u_") == 18
assert "nmi_if" not in interfaces
assert "soc_nmi" not in interfaces
assert "assign s_slv_sel_d[17] = u_i2c1_rib_if.valid;" in routes
assert "assign s_xpi_region_sel[1] = (rib.addr <= `SOC_ADDR_FLASH_END);" in routes
assert "assign u_sdio_rib_if.valid = 1'b0;" in routes
assert gpio.count("// GPIO") == 64
assert "assign u_uart1_if.rx_i = u_gpio_if.di_i[0];" in gpio
assert "assign u_gpio_if.alt1_do_i[22] = u_psram_if.nss_o[0];" in gpio
assert apb_interfaces.count("apb4_if u_") == 10
assert "apb4_pure_if u_archinfo_apb_pure_if ();" in apb_interfaces
assert "assign tmr.paddr = nmi.addr;" in apb_routes
assert "assign tmr.paddr = rib.addr;" in apb_routes
assert "({32{s_psel_q[8]}} & tmr.prdata)" in apb_response
assert "localparam int NSLV = 10;" in apb_declarations
assert fabric.count("nmi_if u_") == 5
assert ".mgmt_nmi(u_mgmt_nmi_if)" in bus_fabric
assert ".user_nmi(u_user_nmi_if)" in bus_fabric
assert ".apb_nmi(u_apb_nmi_if)" in bus_fabric
assert fabric.count("rib_if u_") == 5
assert ".mgmt_rib(u_mgmt_rib_if)" in bus_fabric
assert ".user_rib(u_user_rib_if)" in bus_fabric
assert ".apb_rib(u_apb_rib_if)" in bus_fabric
assert ".rib(u_rib_if)" in bus_fabric
assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
assert "`define SOC_IRQ_NMI_WIDTH 10" in irq_config
assert "`define SOC_IRQ_RIB_WIDTH 10" in irq_config
assert "`define SOC_IRQ_APB_WIDTH 7" in irq_config
assert "assign irq_o[0] = u_clint_if.sfr_irq_o;" in nmi_irq
assert "assign irq_o[0] = u_clint_if.sfr_irq_o;" in rib_irq
assert "assign irq_o[5] = u_tmr_if.irq_o;" in apb_irq
assert "s_irq[16] = s_apb_irq[6];" in irq_wiring
assert "irq_i[31] == 1'b0" in irq_sva
@@ -114,16 +117,16 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
for interrupt in document["interrupts"]
]
assert mappings[:17] == [
("clint_software", "nmi", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "nmi", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "nmi", 2, 2, "uart.irq_o"),
("timer0", "nmi", 3, 3, "s_tim0_irq"),
("timer1", "nmi", 4, 4, "s_tim1_irq"),
("psram", "nmi", 5, 5, "psram.irq_o"),
("spisd", "nmi", 6, 6, "spisd.irq_o"),
("i2c0", "nmi", 7, 7, "i2c0.irq_o"),
("i2s", "nmi", 8, 8, "i2s.irq_o"),
("xpi", "nmi", 9, 9, "xpi.irq_o"),
("clint_software", "rib", 0, 0, "u_clint_if.sfr_irq_o"),
("clint_timer", "rib", 1, 1, "u_clint_if.tmr_irq_o"),
("uart0", "rib", 2, 2, "uart.irq_o"),
("timer0", "rib", 3, 3, "s_tim0_irq"),
("timer1", "rib", 4, 4, "s_tim1_irq"),
("psram", "rib", 5, 5, "psram.irq_o"),
("spisd", "rib", 6, 6, "spisd.irq_o"),
("i2c0", "rib", 7, 7, "i2c0.irq_o"),
("i2s", "rib", 8, 8, "i2s.irq_o"),
("xpi", "rib", 9, 9, "xpi.irq_o"),
("uart1", "apb", 0, 10, "uart.irq_o"),
("pwm", "apb", 1, 11, "pwm.irq_o"),
("ps2", "apb", 2, 12, "ps2.irq_o"),
@@ -141,8 +144,8 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
formal_design = (ROOT / "rtl/mini/formal/nmi2apb_formal.sv").read_text(encoding="utf-8")
formal_properties = (ROOT / "rtl/mini/formal/nmi2apb_formal_props.v").read_text(
formal_design = (ROOT / "rtl/mini/formal/rib2apb_formal.sv").read_text(encoding="utf-8")
formal_properties = (ROOT / "rtl/mini/formal/rib2apb_formal_props.v").read_text(
encoding="utf-8"
)
@@ -155,29 +158,29 @@ def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
assert "wire [ 9:0] psel_comb" in formal_properties
def test_topology_rejects_unknown_or_non_native_regions(tmp_path: Path) -> None:
def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["native_targets"][0]["regions"] = ["UNKNOWN"]
document["rib_targets"][0]["regions"] = ["UNKNOWN"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "unknown region" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["native_targets"][0]["regions"] = ["SRAM"]
document["rib_targets"][0]["regions"] = ["SRAM"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "not an active native region" in result.stderr
assert "not an active rib region" in result.stderr
def test_topology_rejects_duplicate_region_and_disabled_owner(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["native_targets"][1]["regions"] = ["NMI_UART0"]
document["rib_targets"][1]["regions"] = ["RIB_UART0"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "multiple targets" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["native_targets"][15]["regions"] = ["NMI_SDIO"]
document["rib_targets"][15]["regions"] = ["RIB_SDIO"]
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "disabled but declares regions" in result.stderr
@@ -225,16 +228,16 @@ def test_topology_rejects_invalid_gpio_coverage_and_expression(tmp_path: Path) -
def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> None:
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["irq_groups"][1]["name"] = "nmi"
document["irq_groups"][1]["name"] = "rib"
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "interrupt group nmi is duplicated" in result.stderr
assert "interrupt group rib is duplicated" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["interrupts"][1]["group_bit"] = 0
result = validate(write_invalid_topology(tmp_path, document))
assert result.returncode != 0
assert "interrupt group nmi bit 0 is duplicated" in result.stderr
assert "interrupt group rib bit 0 is duplicated" in result.stderr
document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
document["interrupts"][1]["core_bit"] = 0
@@ -288,7 +291,7 @@ def test_generated_irq_wiring_preserves_the_expected_core_vector(tmp_path: Path)
assert "SoC topology IRQ routing test passed" in result.stdout
def test_generated_nmi_routes_select_and_return_the_expected_target(tmp_path: Path) -> None:
def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Path) -> None:
iverilog = shutil.which("iverilog")
sv2v = shutil.which("sv2v")
vvp = shutil.which("vvp")
@@ -312,7 +315,7 @@ def test_generated_nmi_routes_select_and_return_the_expected_target(tmp_path: Pa
topology_output = tmp_path / "topology"
generate(topology_output)
source_list = tmp_path / "soc_topology_nmi.fl"
source_list = tmp_path / "soc_topology_rib.fl"
source_list.write_text(
"\n".join(
[
@@ -320,15 +323,15 @@ def test_generated_nmi_routes_select_and_return_the_expected_target(tmp_path: Pa
f"+incdir+{memory_map_output / 'rtl'}",
f"+incdir+{topology_output / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/nmi_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "tests/rtl/soc_topology_nmi_tb.sv"),
str(ROOT / "tests/rtl/soc_topology_rib_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "soc_topology_nmi_tb.v"
converted = tmp_path / "soc_topology_rib_tb.v"
subprocess.run(
[
sys.executable,
@@ -340,13 +343,13 @@ def test_generated_nmi_routes_select_and_return_the_expected_target(tmp_path: Pa
],
check=True,
)
simulation = tmp_path / "soc_topology_nmi_tb"
simulation = tmp_path / "soc_topology_rib_tb"
subprocess.run(
[
iverilog,
"-g2012",
"-s",
"soc_topology_nmi_tb",
"soc_topology_rib_tb",
"-o",
str(simulation),
str(converted),
@@ -354,4 +357,4 @@ def test_generated_nmi_routes_select_and_return_the_expected_target(tmp_path: Pa
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
assert "SoC topology NMI routing test passed" in result.stdout
assert "SoC topology RIB routing test passed" in result.stdout
tests/test_sta_constraints.py
+9 -1
View File
@@ -15,6 +15,7 @@ ROOT = Path(__file__).resolve().parents[1]
DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
GENERATOR = ROOT / "sta/opensta/generate_sdc.py"
OPENSTA_MAKEFILE = ROOT / "sta/opensta/opensta.mk"
GF180_GENERATOR = ROOT / "pdk/generate_gf180_liberty.py"
ICS55_PREPARER = ROOT / "pdk/prepare_ics55_liberty.py"
ICS55_SIM_MODEL_PREPARER = ROOT / "pdk/prepare_ics55_sim_model.py"
@@ -47,13 +48,20 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
assert "create_generated_clock -name clk_system" in sdc
assert "create_clock -name clk_audio -period 54.253472222" in sdc
assert "create_clock -name clk_dvp -period 41.666666667" in sdc
assert "u_dvp_pclk_clk_buf/clk_o" in sdc
assert "get_pins -quiet" in sdc
assert "u_retrosoc.u_ip_rib_wrapper/u_rib_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
assert "-group [get_clocks {clk_external clk_system}]" in sdc
assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
assert "set_input_transition" not in sdc
assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
def test_opensta_invocation_exits_after_a_tcl_error() -> None:
makefile = OPENSTA_MAKEFILE.read_text(encoding="utf-8")
assert "$(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS)" in makefile
def test_core_sdc_rejects_pads_missing_from_the_pin_map(tmp_path: Path) -> None:
document = json.loads(DOMAINS.read_text(encoding="utf-8"))
document["domains"][3]["sta"]["source_port"] = "missing_pad"
tests/test_user_extensions.py
+2 -2
View File
@@ -48,8 +48,8 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
assert core.count("nmi_if u_user_") == 6
assert "nmi.valid = '0;" in core
assert core.count("rib_if u_user_") == 6
assert "rib.valid = '0;" in core
assert "5'd0: begin" in core
assert "5'd5: begin" in core
assert "core_reset_i[0]" in core