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https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: reassign all mmio ip addrs
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2 files changed
+69
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+30
-26
@@ -581,39 +581,43 @@ void print_reg(char *info, uint32_t val, int digits)
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void ip_counter_timer_test()
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{
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print("[IP] counter timer test\n");
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print_reg("[TIM VALUE] ", reg_timer_value, 8);
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print_reg("[TIM CONFIG] ", reg_timer_config, 8);
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print_reg("[TIM0 VALUE] ", reg_timer0_value, 8);
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print_reg("[TIM0 CONFIG] ", reg_timer0_config, 8);
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print_reg("[TIM1 VALUE] ", reg_timer1_value, 8);
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print_reg("[TIM1 CONFIG] ", reg_timer1_config, 8);
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reg_timer_value = (uint32_t)0xffffffff;
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// reg_timer_config = 1;
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// reg_timer_config = 2;
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// reg_timer_config = 4; // One-shot mode, where the counter triggers an interrupt when it reaches the value of reg_timer_data
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reg_timer_config = 8; // 1000, timer enable, continuous mode, count down, irq disable
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// reg_timer_config = 15;
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reg_timer0_value = (uint32_t)0xffffffff;
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reg_timer0_config = (uint32_t)0x0001; // irq disable, count down, continuous mode, timer enable
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print_reg("[TIM VALUE] ", reg_timer_value, 8);
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print_reg("[TIM CONFIG] ", reg_timer_config, 8);
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reg_timer1_value = (uint32_t)0x0000ffff;
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reg_timer1_config = (uint32_t)0x0101; // irq disable, count up, continuous mode, timer enable
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print_reg("[TIM0 VALUE] ", reg_timer0_value, 8);
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print_reg("[TIM0 CONFIG] ", reg_timer0_config, 8);
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print_reg("[TIM1 VALUE] ", reg_timer1_value, 8);
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print_reg("[TIM1 CONFIG] ", reg_timer1_config, 8);
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for (int i = 0; i < 10; ++i)
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{
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print_reg("[TIM DATA] ", reg_timer_data, 8);
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print_reg("[TIM0 DATA] ", reg_timer0_data, 8);
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print_reg("[TIM1 DATA] ", reg_timer1_data, 8);
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}
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}
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void ip_gpio_test()
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{
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print("[IP] gpio test\n");
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reg_gpio_pub = 0x5a5a; // NOT(pullup)
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reg_gpio_enb = 0xa5a5; // NOT(output enable)
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reg_gpio_data = 0xffff;
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reg_gpio_data = 0x0000;
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for (int i = 0; i < 10; ++i)
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{
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print("[GPIO] ");
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print_hex(reg_gpio_data, 7);
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print("\n");
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}
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print_reg("[GPIO ENB] ", reg_gpio_enb, 8);
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reg_gpio_enb = (uint32_t)0x0000;
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print_reg("[GPIO ENB] ", reg_gpio_enb, 8);
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print_reg("[GPIO DATA] ", reg_gpio_data, 8);
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reg_gpio_data = (uint32_t)0xffff;
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print_reg("[GPIO DATA] ", reg_gpio_data, 8);
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reg_gpio_data = (uint32_t)0x0000;
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print_reg("[GPIO DATA] ", reg_gpio_data, 8);
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}
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void i2c_init(unsigned int pre)
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@@ -687,14 +691,14 @@ void main()
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// print("\n");
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// cmd_read_flash_id();
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// cmd_read_flash_regs();
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cmd_print_spi_state();
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// cmd_print_spi_state();
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ip_counter_timer_test();
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// ip_gpio_test();
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// ip_counter_timer_test();
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ip_gpio_test();
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ip_i2c_test();
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cmd_benchmark(true, 0);
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// cmd_benchmark(true, 0);
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// cmd_benchmark_all();
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cmd_memtest();
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// cmd_memtest();
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cmd_echo();
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while (1)
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;
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+39
-30
@@ -4,45 +4,54 @@
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#include <stdint.h>
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#include <stdbool.h>
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// memory map definitions
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// memory map io definitions
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#define reg_spictrl (*(volatile uint32_t*)0x02000000)
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#define reg_uart_clkdiv (*(volatile uint32_t*)0x03000078)
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#define reg_uart_data (*(volatile uint32_t*)0x0300007c)
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// NOTE: "config" subsumes "control" and "prescale" fields.
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#define reg_i2c_config (*(volatile uint32_t*)0x030000d4)
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#define reg_i2c_control (*(volatile uint16_t*)0x030000d6)
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#define reg_i2c_prescale (*(volatile uint16_t*)0x030000d4)
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// NOTE: "status" and "command" are the same byte (one read, one write)
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#define reg_i2c_status (*(volatile uint32_t*)0x030000d8)
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#define reg_i2c_command (*(volatile uint32_t*)0x030000d8)
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#define reg_i2c_data (*(volatile uint32_t*)0x030000dc)
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#define reg_timer_config (*(volatile uint32_t*)0x030000f4)
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#define reg_timer_value (*(volatile uint32_t*)0x030000f8)
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#define reg_timer_data (*(volatile uint32_t*)0x030000fc)
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#define reg_spi_config (*(volatile uint32_t*)0x030000b8)
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#define reg_spi_data (*(volatile uint32_t*)0x030000bc)
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#define reg_gpio_data (*(volatile uint32_t*)0x03000000)
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#define reg_gpio_enb (*(volatile uint32_t*)0x03000004)
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#define reg_gpio_pub (*(volatile uint32_t*)0x03000008)
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#define reg_gpio_pdb (*(volatile uint32_t*)0x0300000c)
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#define reg_spi_commconfig (*(volatile uint32_t*)0x03000080)
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#define reg_spi_enables (*(volatile uint32_t*)0x03000084)
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#define reg_spi_pll_config (*(volatile uint32_t*)0x03000088)
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#define reg_spi_mfgr_id (*(volatile uint32_t*)0x0300008c)
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#define reg_spi_prod_id (*(volatile uint32_t*)0x03000090)
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#define reg_spi_mask_rev (*(volatile uint32_t*)0x03000094)
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#define reg_spi_pll_bypass (*(volatile uint32_t*)0x03000098)
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#define reg_uart_clkdiv (*(volatile uint32_t*)0x03000010)
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#define reg_uart_data (*(volatile uint32_t*)0x03000014)
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#define reg_xtal_out_dest (*(volatile uint32_t*)0x030000a0)
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#define reg_pll_out_dest (*(volatile uint32_t*)0x030000a4)
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#define reg_trap_out_dest (*(volatile uint32_t*)0x030000a8)
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#define reg_spi_commconfig (*(volatile uint32_t*)0x03000018)
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#define reg_spi_enables (*(volatile uint32_t*)0x0300001c)
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#define reg_spi_pll_config (*(volatile uint32_t*)0x03000020)
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#define reg_spi_mfgr_id (*(volatile uint32_t*)0x03000024)
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#define reg_spi_prod_id (*(volatile uint32_t*)0x03000028)
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#define reg_spi_mask_rev (*(volatile uint32_t*)0x0300002c)
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#define reg_spi_pll_bypass (*(volatile uint32_t*)0x03000030)
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#define reg_irq7_source (*(volatile uint32_t*)0x030000b0)
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#define reg_irq8_source (*(volatile uint32_t*)0x030000b4)
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#define reg_xtal_out_dest (*(volatile uint32_t*)0x03000034)
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#define reg_pll_out_dest (*(volatile uint32_t*)0x03000038)
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#define reg_trap_out_dest (*(volatile uint32_t*)0x0300003c)
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#define reg_irq7_source (*(volatile uint32_t*)0x03000040)
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#define reg_irq8_source (*(volatile uint32_t*)0x03000044)
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#define reg_spi_config (*(volatile uint32_t*)0x03000048)
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#define reg_spi_data (*(volatile uint32_t*)0x0300004c)
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// NOTE: "config" subsumes "control" and "prescale" fields.
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#define reg_i2c_config (*(volatile uint32_t*)0x03000050)
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#define reg_i2c_prescale (*(volatile uint16_t*)0x03000050)
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#define reg_i2c_control (*(volatile uint16_t*)0x03000052)
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// NOTE: "status" and "command" are the same byte (one read, one write)
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#define reg_i2c_status (*(volatile uint32_t*)0x03000054)
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#define reg_i2c_command (*(volatile uint32_t*)0x03000054)
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#define reg_i2c_data (*(volatile uint32_t*)0x03000058)
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#define reg_timer0_config (*(volatile uint32_t*)0x0300005c)
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#define reg_timer0_value (*(volatile uint32_t*)0x03000060)
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#define reg_timer0_data (*(volatile uint32_t*)0x03000064)
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#define reg_timer1_config (*(volatile uint32_t*)0x03000068)
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#define reg_timer1_value (*(volatile uint32_t*)0x0300006c)
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#define reg_timer1_data (*(volatile uint32_t*)0x03000070)
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// archinfo
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// rng
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//
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// command register bits
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// bit 7 = start
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