- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks.
- Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory.
- Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure.
- Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency.
- Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure.
- Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.
- Removed UART files from clusterip and updated file lists accordingly.
- Added new UART flow control module and interface to manage RTS/CTS signals.
- Updated UART formal verification files to include new flow control signals.
- Modified UART testbench to validate flow control behavior and updated test cases.
- Adjusted top-level design to integrate new UART interface and signal connections.
- Enhanced GPIO pin mapping to accommodate new UART control signals.
- Updated linting and formal generation scripts to reflect changes in UART structure.
- Deleted the UART interface and related components from the RTL design, including the UART TX/RX signals and instances.
- Removed the timer interface and its associated files from the project, including the timer definitions and references in the integration files.
- Updated the APB target configurations to reflect the removal of the UART and timer components, ensuring the IRQ and memory map configurations are consistent.
- Adjusted the formal verification properties and testbenches to exclude references to the removed components.
- Cleaned up the integration documentation to accurately describe the current state of the system without the UART and timer interfaces.
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Introduced for handling QSPI flash memory operations, including command and address handling.
- Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C.
- Created for the flash memory implementation, supporting initialization, reading, and memory copying.
- Updated to integrate the new QSPI Flash module and connect it with the existing system.
- Refactored file paths in various filelists and scripts to accommodate the new directory structure under .
- Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure.
- Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
maksyuki