- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks.
- Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory.
- Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.
- Deleted references to XEZIM and CVC in the Makefile and related scripts.
- Removed XEZIM-specific and CVC-specific files, including external memory models and SRAM models.
- Updated the test suite to reflect the removal of XEZIM and CVC simulators, ensuring no broken references remain.
- Cleaned up the README and doctor scripts to remove mentions of XEZIM and CVC.
- Updated the testbench to conditionally include pull-up resistors and reset hold time based on the selected simulator.
- Enhanced the filelist generation script to support both XEZIM and CVC formats, allowing for simulator-specific options and exclusions.
- Introduced new makefiles ( and ) to handle compilation and simulation for the respective backends.
- Added external memory models and SRAM models specifically for XEZIM simulations.
- Created a test suite to validate the integration of optional simulator backends and ensure they do not interfere with the default backend.
- Updated README.md to clarify the status of KianV RV32IMA and PicoRV32 in the user-extension map.
- Modified Makefile to include USER_EXTENSIONS_SOURCE in MPW variant stamp dependencies.
- Enhanced integration README.md to better describe the relationship between user_extensions.json and mpw.toml.
- Updated generate_user_extensions.py to include design_id in ExtensionTarget and enforce unique design IDs.
- Changed user_extensions.json schema version to 2 and added design_id fields for core and IP targets.
- Refactored generate_mpw.py to support the new manifest structure and validate design selections.
- Adjusted sysctrl_tb.sv test cases to reflect changes in user core reset states.
- Enhanced test_opipsram.py to utilize ccache for improved compilation performance.
- Updated test_script_tools.py to include new tests for active manifest generation.
- Modified test_user_extensions.py to validate isolated scalar bindings and reject duplicate design selections.
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
- Updated filelist to include new XPI source files.
- Modified IRQ compatibility mapping for XPI in the SOC topology generator.
- Adjusted JSON topology configuration to reflect new IRQ signal naming.
- Changed software.mk to reference the new XPI HAL source file.
- Enhanced APB4 peripheral module to include XPI IRQ signal.
- Updated RTL style audit to include new XPI files.
- Documented new XPI programming script in README.
- Added a new script for programming XPI flash through OpenOCD.
- Enhanced XPI IO testbench to validate new LUT engine and isolation behavior.
- Created unit tests for the new XPI programming tool and its functionalities.
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6.
- Added new testbench for SPI-SD clock functionality (spisd_clock_tb).
- Introduced testbench for SPI-SD command engine (spisd_command_tb).
- Created testbench for SPI-SD CRC calculation (spisd_crc_tb).
- Implemented testbench for SPI-SD data handling (spisd_data_tb).
- Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb).
- Added Python test suite for SPI-SD RTL regressions (test_spisd.py).
- Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions.
- Updated to include IRQ handling for SDIO0 and SDIO1.
- Enhanced to account for performance management of SDIO0 and SDIO1.
- Modified memory map tests to include SDIO base addresses and performance wait offsets.
- Updated pin mapping tests to include SDIO1 signals.
- Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations.
- Added a new test for verifying SDIO register parity against the RTL definition.
- Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
- Updated memory map tests to include OPI PSRAM address and size definitions.
- Introduced new test suite for OPI PSRAM to ensure RTL and HAL ABI consistency.
- Enhanced script tools tests to validate formal filelists for OPI PSRAM.
- Modified SOC topology tests to incorporate OPI PSRAM bindings and IRQ mappings.
- Introduced to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.
- Introduced burst length handling in the SDRAM Verilator model, allowing for more flexible read/write operations.
- Added new SDRAM-related source files to the project structure, including sdram_pkg.sv and sdram_axi4.sv.
- Updated software makefile to include new SDRAM-related C source files for HAL.
- Enhanced C test suite with new tests for SDRAM timing and functionality, ensuring proper integration with the HAL.
- Improved RTL testbench for SDRAM, adding support for burst writes and reads, and verifying data integrity.
- Updated Python test scripts to reflect changes in SDRAM handling and ensure comprehensive coverage of SDRAM functionality.
- Added checks to ensure register offsets between RTL and HAL definitions match, maintaining consistency across the codebase.
- Updated the PSRAM register module to include additional signals for better control and data management.
- Introduced dedicated signals for each register's data and enable lines, enhancing clarity and maintainability.
- Replaced synchronous assignments with combinational logic for register updates.
- Added new D flip-flops for various control signals to ensure proper synchronization.
- Improved the performance control logic to reset counters based on specific conditions.
- Minor formatting adjustments in the I2S register and APB4 I2S modules for consistency.
- Updated test script to include additional utility files for comprehensive testing.
- Updated filelist to include I2S related files.
- Enhanced formal file generation script to support I2S target.
- Introduced I2S formal design and properties for verification.
- Modified formal makefile to include I2S targets and source files.
- Added I2S related source files to software build.
- Updated style audit to include I2S files.
- Implemented I2S helper functions in C tests.
- Created I2S testbench for RTL simulation.
- Added regression test for I2S controller functionality.
- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.
- Introduced SYNTH_RECIPE variable to select between balanced, area, and speed synthesis recipes.
- Updated Makefile to handle new SYNTH_RECIPE variable and its validation.
- Modified synthesis scripts to utilize the selected recipe, ensuring outputs are directed to the appropriate directories.
- Enhanced documentation to reflect changes in synthesis flow and directory structure.
- Added tests to verify correct behavior of new synthesis recipes and their integration into the regression suite.
- Removed obsolete scripts and configurations related to previous synthesis methods.
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface.
- Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files.
- Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests.
- Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
- Updated formal.mk to include PSRAM in formal verification targets and source files.
- Modified software.mk to include psram_math.c for HAL.
- Enhanced pin_map.json to map GPIO pins for PSRAM control signals.
- Refactored ip_ribp_wrapper.sv to integrate PSRAM interface and remove unused ribp interfaces.
- Updated rtl_style_audit.json to include PSRAM related files.
- Added PSRAM testbench (psram_tb.sv) for integration testing.
- Created test_psram.py to validate PSRAM controller functionality and register offsets.
- Adjusted memory map tests to reflect new PSRAM address space and size.
- Enhanced the RTL style checker script to include new diagnostic rules for function declarations, primary design units, and synthesis exclusions.
- Added functions to handle audit issues, ensuring that the audit records match the current inventory of RTL files.
- Updated test cases to reflect changes in RTL file names and paths, ensuring consistency with the new naming conventions.
- Introduced additional tests for style violations, including mismatched primary design units and synthesizable initial blocks.
- Adjusted file paths in various test files to align with the new RTL structure and naming conventions.
- Introduced common setup script for Yosys () to manage global variables and configurations.
- Added output filtering script () to enhance log readability.
- Created technology initialization script () for handling different PDKs.
- Developed main synthesis script () to orchestrate the synthesis flow using Yosys.
- Added a configuration makefile () for synthesis settings.
- Updated Yosys makefile () to integrate new scripts and configurations.
- Adjusted paths in and RTL filelists to reflect new directory structure under .
- Modified various scripts and test files to accommodate the new PDK paths and ensure compatibility.
- Enhanced warning normalization in the analysis script to preserve PDK signatures.
- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types.
- Introduced address generation logic for read and write operations based on burst parameters.
- Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol.
- Modified the SDRAM controller and testbench to accommodate the new burst handling features.
- Enhanced test cases to verify the correct behavior of burst transactions and address patterns.
- Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.
- Changed parameter names in various modules from uppercase to camel case for consistency.
- Updated local parameters in testbenches to follow the same naming convention.
- Modified the RTL style manifest to include additional prefixes for better organization.
- Enhanced the check_format and check_rtl_style scripts to improve file tracking and naming validation.
- Added new tests to ensure compliance with the updated naming conventions and allowed local parameters in specific contexts.
- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure.
- Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency.
- Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure.
- Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.
- Renamed parameters and signals for better clarity (e.g., DVP_PAYLOAD_WIDTH to DvpPayloadWidth).
- Updated signal assignments and logic to maintain consistent naming conventions.
- Changed output signal names in DVP_CAMERA and DVP_CORE modules to follow a unified naming scheme.
- Adjusted the configuration and command handling in dvp_reg and dvp_core modules to reflect new naming.
- Enhanced the formal verification module to align with updated signal names.
- Ensured all changes maintain functionality while improving code maintainability.
- Updated to enforce stricter naming rules for new owned RTL.
- Expanded documentation on RTL coding style to include detailed naming contracts.
- Refactored RTL code to comply with new naming conventions, including:
- Renaming typedefs to use suffix for enums and for other types.
- Ensuring module names use lower snake case and ports have appropriate direction suffixes.
- Adjusting instance names to start with and ensuring state variables use and suffixes.
- Modified scripts to include checks for new naming rules and updated tests to validate these changes.
- Updated to reflect new naming guidelines and exceptions.
- Updated multiple modules to enhance code formatting and readability by breaking long lines and aligning conditions.
- Improved comments for clarity in , , and .
- Added checks in to reject forbidden constructs such as , non-ASCII characters, and lines exceeding 100 characters.
- Introduced unit tests to validate style checks for forbidden constructs and non-ASCII characters.
- Modified dma_core to accommodate a wider data width for FIFO operations.
- Updated filelists to include new DVP source files and formal verification files.
- Introduced formal verification modules for DVP functionality.
- Enhanced clock and reset domain configurations for DVP integration.
- Added DVP interrupt handling in the IRQ topology.
- Implemented a testbench for DVP to validate register access and frame processing.
- Updated software build scripts to include DVP-related source files.
- Adjusted the system topology to reflect the new DVP interrupt and IRQ mapping.
- Renamed error signals in rib2ribp, rib_error_slave, ribp2axi4, and ribp2rib modules for consistency.
- Updated state machine logic to use new error signal names.
- Enhanced RTL style checking scripts to enforce naming conventions and positional parameter connections.
- Introduced migration scripts to convert positional instances to named connections and shorten local identifiers.
- Added tests to validate migration scripts and ensure correct functionality.
- Introduced a comprehensive RTL coding style document at detailing naming conventions, module structure, formatting, and ownership boundaries.
- Updated to reference the new coding style document and clarify the python3 /nfs/share/home/miaoyuchi/retroSoC/scripts/check_rtl_style.py --root /nfs/share/home/miaoyuchi/retroSoC \
--profile owned --changed-only --verible-verilog-lint verible-verilog-lint
rtl-style-check: owned passed (0 baseline findings) process.
- Refactored several RTL modules in to adhere to the new naming conventions for clock and reset signals.
- Created to define profiles for owned, verification, and technology RTL sources, including suffixes and linting rules.
- Developed to check for compliance with the ownership-aware RTL style rules, focusing on positional connections and legacy constructs.
- Added tests in to validate the functionality of the RTL style checker.
- Updated to document the new style checking script and its usage.
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated and to reflect changes in bus naming conventions.
- Enhanced to include AXI4-Stream interface checks and validate stream data transfers.
- Modified to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
- Removed UART files from clusterip and updated file lists accordingly.
- Added new UART flow control module and interface to manage RTS/CTS signals.
- Updated UART formal verification files to include new flow control signals.
- Modified UART testbench to validate flow control behavior and updated test cases.
- Adjusted top-level design to integrate new UART interface and signal connections.
- Enhanced GPIO pin mapping to accommodate new UART control signals.
- Updated linting and formal generation scripts to reflect changes in UART structure.
maksyuki