- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Updated tiny-soc.md to reflect the 2026-10-07 refreeze, establishing ICS55 as the default target PDK with HAVE_PLL=YES.
- Added detailed sections on final timing gate policies, PLL integration, and execution order for Tiny SoC.
- Modified soc-family-positioning.md to indicate the new default target for Tiny as ICS55/PLL while maintaining IHP130 compatibility.
- Enhanced pdk/README.md and setup.py to support the integration of the locked ICS55 PLL views, including setup commands and validation.
- Introduced tests for the ICS55 PLL dependency to ensure proper integration and validation of PLL views.
- Updated rtl/tiny/README.md to clarify the current executable baseline and the pending integration of ICS55.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling.
- Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels.
- Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses.
- Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic.
- Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.
- Updated the tiny-soc-verification.md to clarify the separation of PIO-lite as a standard-product extension, detailing its planned features and evidence requirements.
- Revised tiny-soc.md to emphasize the historical context of the R2 design freeze and the independent nature of the PIO-lite extension, including its integration requirements and phase structure.
- Added details in soc-family-positioning.md regarding the PIO-lite extension's capabilities and its distinction from the R2 performance-only approval.
- Enhanced README.md files in rtl/ip and rtl/tiny to reflect the future integration of the PIO-lite extension, specifying its features and the implications for existing RTL and DMA configurations.
- Clarified integration details for WS2812 and XPI in respective documentation.
- Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels.
- Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts.
- Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
- Added details on the Tiny Gen1 target's shared XPI register/LUT/PHY contract and optional NSS1 PSRAM integration.
- Clarified the memory model to include optional initialized XPI NSS1 PSRAM for whole-frame data.
- Updated the edge I/O section to reflect the alternate DVP V2 camera profile and GPIO allocations.
- Revised the shared services and package specifications to align with the latest P10 refreeze.
- Enhanced the README to include P10 documentation refreeze details, emphasizing DVP V2 contract and PSRAM integration.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets.
- Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations.
- Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details.
- Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
- Introduced a new maintenance reference for dependency and environment routing.
- Enhanced the feature implementation skill with migration references for behavior-preserving changes.
- Added regression and RTL migration references to support feature review processes.
- Created a new physical flow skill with detailed execution and recovery guidelines.
- Updated evals for feature implementation and review skills to include new scenarios.
- Improved the AGENTS.md and tests to reflect the new skills and references.
- Added new skills for retroSoC feature implementation and review, including YAML configurations and evaluation cases.
- Removed deprecated mini feature design and implementation skills.
- Updated documentation to reflect changes in skill names and functionalities.
- Adjusted test cases to ensure compatibility with the new skill structure and validate the presence of required files and metadata.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities.
- Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi.
- Enhanced register reference parsing to accommodate Tiny-specific memory maps.
- Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs.
- Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims.
- Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Clarified P5 capabilities including direct/ring WAV/FLAC jobs and new KWS model integration.
- Specified requirements for evidence acceptance related to P5 enhancements.
- Noted that P6 MP3 support remains deferred with emphasis on design requirements.
- Updated details on P9 refreeze requirements, including macro-backed storage and future obligations.
- Reinforced that existing system clock/reset/IRQ/resource assignments remain unchanged.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced to define the development environment and validate runtime/platform contracts.
- Enhanced with to ensure change markers adhere to publication rules.
- Updated to integrate boot acceptance checks and ensure dependencies are correctly managed.
- Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards.
- Implemented checks in to validate the presence of development environment dependencies.
- Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
- Modified waveforms.json to reflect changes in resource tracking from nine to ten positions for both resource-controller integration and reference monitor parameters.
- Enhanced dev_reference.py to include NPU sources and updated CI snapshot validation to accommodate new statuses and conclusions.
- Added example NPU implementation in npu.c for job submission and result handling.
- Updated format_reference.py to validate NPU descriptor word offsets against RTL definitions.
- Adjusted storage_reference.py to reflect changes in APU and NPU local memory configurations.
- Enhanced system_reference.py to include NPU implementation details and validate accelerator claims.
- Updated tests to reflect changes in the structure and coverage of NPU and APU components, ensuring accurate validation of configurations and claims.
- Introduced new tests in v05.py to ensure distinct handling of executable configurations and evidence for NPU and APU.
- Introduced for deterministic corpus framing, CRC checks, and regression evidence for NPU-P6.
- Added to validate NPU-P6 reference execution.
- Created a new RTL model for gate-level NPU transactions.
- Updated to instantiate and streamline the testbench.
- Enhanced with capability checks and added NPU-P6 reference contract tests.
- Modified to include in the source list and refactor rejection logic.
- Updated README.md to document new test scripts and their purposes.
- Introduced differential tests for the APU-P7 frontend profile-1 BAM to ensure consistency with ROM and generator outputs.
- Implemented concurrent decode and continuous KWS smoke tests for APU-P7 to validate system stability under load.
- Added accuracy qualification tests for APU-P7 to verify through-hardware performance against expected results.
- Created contention tests for APU-P8 to assess USB2/SDIO0/APU Gateway A interactions.
- Developed quiesced loader admission tests for APU-P8 to ensure proper handling of DMA operations.
- Added post-fault visibility tests for APU-P8 HP interconnect to confirm fault handling capabilities.
- Enhanced register parity tests to include ABI digest verification for consistency across implementations.
- Updated publication register tests to reflect changes in capability constants for P5 and P7 profiles.
- Removed unsupported fault handling from and replaced it with a test for average pooling execution.
- Updated the test for unsupported placements to validate average pooling and depthwise convolution placements.
- Introduced new tests for softmax functionality in , including parameter validation and edge cases.
- Added qualification tests to ensure rejection of common-mode numerical errors and incomplete runs in .
- Enhanced RTL tests to cover memory downsizing and kernel burst capabilities in and .
- Adjusted boot status assertions in to reflect updated expected values.
This commit includes new shell source files for the NPU, specifically:
- npu_mac_array.sv
- npu_accumulator.sv
- npu_vector.sv
- npu_requantizer.sv
These additions aim to improve the testing coverage and functionality of the NPU RTL shell.
- Introduced scoped typography rules for compact cells and emphasized labels in the SoC functional overview.
- Updated the diagram to utilize new typography settings, including size adjustments for CDC and Gateway labels.
- Implemented geometry validation for SoC diagrams to ensure proper routing and clearance between elements.
- Added comprehensive tests for geometry validation, PDF typography checks, and compact text handling.
- Created new Python modules for shared geometry and PDF-bound typography checks to streamline validation processes.
- Enhanced documentation to clarify typography requirements and routing styles for SoC diagrams.
- Added validation checks for GA2D soft reset and error handling in .
- Improved resource controller tests in to cover IRQ routing and ownership scenarios.
- Updated performance log tests in to reflect changes in GA2D features and formats.
- Introduced a new netlist transaction test for GA2D in to ensure synthesized block functionality.
- Modified publication software tests in to account for new GA2D stages.
- Adjusted script tools tests in for updated configuration values.
- Added print statements for better traceability in GA2D reference campaign tests.
This commit introduces a comprehensive set of unit tests for the NPU-P3 job execution, covering the DMA engine, job decoder, and core functionalities. The tests utilize Icarus and Verilator for simulation and include descriptor validation, fault handling, and various operational scenarios. Key features include:
- Descriptor construction and validation mirroring ABI 1.0.
- Detailed test cases for valid and invalid descriptors.
- Core testbench scenarios for various operations including convolution, pooling, and fully connected layers.
- Integration of golden model comparisons for output verification.
These tests aim to ensure robust functionality and adherence to specifications for the NPU-P3 architecture.
- Introduced to ensure consistency between RTL and C register definitions.
- Implemented exhaustive checks for offsets, scalar encodings, bit shifts, and enumerations.
- Added for shell and control-CDC unit tests using Icarus and Verilator.
- Created test cases for NPU register and control CDC functionality, verifying successful simulation outputs.
- Introduced a new SOC functional architecture diagram in .
- Updated to include instructions for the new SOC diagram, including layout and design specifications.
- Modified to activate changes related to the SOC functional overview.
- Enhanced to include new SOC architecture catalog references.
- Updated to account for the new SOC architecture diagrams in coverage checks.
- Created for validating SOC diagram specifications and ensuring compliance with design rules.
- Added tests in to validate SOC diagram structure and integrity.
- Adjusted existing tests to reflect the addition of SOC architecture coverage.
- Introduced waveform definitions for GA2D operations and exceptions in waveforms.json.
- Added a new Python module for validating CI snapshots and APU implementation details.
- Enhanced diagram coverage validation to ensure accurate reporting of circuit and layout counts.
- Updated programming reference to dynamically calculate read/write credits based on master policies.
- Implemented tests for validating CI snapshot integrity and diagram coverage consistency.
- Added example usage of GA2D fill operation in a new C source file.
- Improved error handling in software reference for IRQ count validation.
- Adjusted diagram reference to check for legacy and version-specific instruction limits.
- Introduced for comprehensive testing of the NPU vector module, covering bias preload, lane-masked accumulation, and fault conditions.
- Created to implement differential tests for NPU compute-core RTL using Icarus Verilog and Verilator, ensuring bit-exact results against a numerical oracle.
- Added to validate NPU memory and patch packer functionality, including SRAM models and various packing scenarios.
- Introduced to validate KWS and VWW locked model graphs against expected configurations, including operator sequences, tensor properties, and model integrity checks.
- Added to cover numerical profiles and validate arithmetic operations, including convolution, depthwise convolution, fully connected layers, and various tensor operations.
- Created to ensure proper setup and validation of NPU-P0 reference flow, including dataset integrity and model hash consistency.
- Implemented error handling tests for malformed buffers and model mutations to ensure robustness.
- Added information about the Mini NPU specification, including its architecture and verification requirements, to rtl/README.md.
- Included details on the frozen NPU contract and its integration considerations in rtl/mini/README.md.
feat/apu splits the instruction limit into APUMC_MAX_INSTRUCTIONS_V1/V2
with APUMC_MAX_INSTRUCTIONS aliasing the V1 value, so the committed
plain '2048' assignment the drift test mutated no longer exists. Mutate
the alias assignment instead; the drift still disagrees with the RTL
define and must be rejected.
- system-reference.json: APU RX stream tready now feeds the KWS engine
(s_kws_rx_ready) instead of a constant 0
- diagram-layouts.json: APUMC header packs the requested abi word and
entry words mask entry_pc/first_pc/last_pc for APUMC V2
- diagram-storage.json: APU control store implements the 4096-word
(32 KiB) V1.1 refreeze
- diagram-circuits.json: pre-existing GA2D master 6 missing from the two
axi4_data_crossbar master_read_limit bindings (broken on dev before
the merge)
- test_script_tools.py: pre-existing whitespace-strict SOC_SIM_TIME
assertion broken by dev's app.mk alignment change (failed on dev
before the merge); use the test's regex idiom
- Adjusted the native JPEG path to reflect one normal read and one normal write credit for master slot 6 in various documentation files, including README.md, datasheets, and programming references.
- Updated the bus programming section to clarify the admission policy and error handling for the JPEG private path.
- Enhanced the media formats and product use sections to specify the implications of the new credit structure on system integration and performance.
- Modified the RTL implementation to ensure proper credit allocation for the JPEG master in the AXI4 data crossbar.
- Updated regression tests to validate the new credit handling and ensure compliance with the updated specifications.
- Increased simulation timeout for Verilator to accommodate new testing requirements.
- Updated testbench and wrapper test cases to reflect GA2D Phase 5 changes.
- Modified Python test scripts to validate Phase 5 functionality and requirements.
- Enhanced DMA tests for byte-accurate coverage in Phase 5.
- Adjusted register parity tests to include Phase 5 capability and limits.
- Updated publication software tests to reference GA2D Phase 5.
- Changed formal target tests to utilize Phase 5 production hierarchy.
- Updated resource_controller_tb.sv to verify resource STATUS bit layout after HP handoff.
- Modified test_ga2d.py to reflect changes for GA2D Phase 4, including memory map generation and source file handling.
- Introduced new test_ga2d_dma.py for independent FILL/COPY reference-model coverage.
- Updated test_ga2d_platform.py to check for the activation of the private AXI64 master and IRQ routing.
- Adjusted test_ga2d_register_parity.py to validate new scalar encodings for Phase 4.
- Enhanced test_hp_boot_bundle.py to ensure HP boot uses the private GA2D mailbox and resource lifecycle.
- Updated test_hp_platform.py to verify GA2D lifecycle markers and cache handshake budget.
- Modified test_performance_log.py to include GA2D workload and configuration facts in performance logs.
- Adjusted test_publication_retrieval.py and test_publication_software.py to reflect changes in GA2D stages.
- Updated test_script_tools.py to ensure GA2D formal filelists are correctly scoped.
- Refactored test_soc_topology.py to validate the private master policy and active shell in GA2D Phase 4.
- Updated resource_controller_tb.sv to include additional checks for IRQ handling and lifecycle states for GA2D resource.
- Modified soc_irq_topology_tb.sv to accommodate 64-bit IRQ vector handling and updated expectations for IRQ routing.
- Introduced test_ga2d.py for directed verification of GA2D Phase 3 APB4 shell functionality.
- Revised test_ga2d_platform.py to reflect changes in GA2D integration and ensure proper IRQ routing.
- Added test_ga2d_register_parity.py to synchronize GA2D RTL and SDK register constants.
- Updated test_lp_irq.py to reflect changes in IRQ allocation and metadata for GA2D.
- Enhanced test_memory_map.py to verify GA2D MMIO region presence in the memory map.
- Adjusted test_publication_software.py to include GA2D in application results.
- Modified test_soc_topology.py to ensure correct topology generation for GA2D, including IRQ and APB bindings.
- Updated onchip_ram64_tb to increase ID_WIDTH from 6 to 7 and adjusted related write/read tasks.
- Modified resource_controller_tb to accommodate an expanded resource count from 8 to 9, updating related logic signals.
- Enhanced sysctrl_tb to introduce new fault handling logic for data plane faults, including additional fault validation and delivery mechanisms.
- Added tests for clock and reset domains to ensure proper handling of data plane faults and their reset contracts.
- Introduced new test_ga2d_platform.py to verify GA2D Phase 2 functionality, including lifecycle and recovery processes.
- Updated test_soc_topology.py to ensure proper data master policies and validate GA2D integration within the system.
- Enhanced sysctrl.py to ensure the fault master retains the high bit for data plane faults.
- Introduced new CSRs for Hazard3 external interrupts in system_csr.h.
- Expanded the IRQ API in irq.h to include external IRQ enable/disable and priority setting functions.
- Implemented external IRQ handling in system_irq_handler.c, including registration, enabling, and dispatching.
- Created a new source file irq_nocsr.c for CSR-disabled firmware, providing stubs for external IRQ functions.
- Updated booter.c to reflect the new external IRQ count in printed specifications.
- Modified the soc_topology generation script to accommodate 64-bit IRQ vectors and external IRQ count.
- Enhanced the integration tests to validate the new IRQ handling and metadata generation.
- Adjusted various files to ensure compatibility with the new external IRQ architecture, including Verilog modules and test cases.
- Added details about the approved GA2D contract and its phased implementation in resource-controller.md.
- Updated lp-hp-architecture.md to reflect the frozen GA2D specification and its implications for product descriptions.
- Enhanced rtl/README.md with information on the Mini GA2D graphics accelerator's architecture and pending implementation.
- Clarified integration requirements in rtl/mini/integration/README.md regarding GA2D's phased changes and their impact on existing allocations.
- Implemented the KWS engine in the RTL and added necessary components including KWS SRAM client and model loader.
- Enhanced the APU ring scheduler testbench to validate KWS descriptors.
- Introduced new Python tests for KWS functionality, including model import validation, inference checks, and error handling for mutated models.
- Updated existing tests to include KWS components and ensure proper integration within the APU architecture.
- Refactored code for clarity and consistency, including adjustments to signal handling and memory management in test cases.
Added a section detailing the export of the PCLK-synchronized RX warm-flush-busy state as
to the APU's . This change addresses the P7
implementation obligation and clarifies the handling of audio resets and KWS mono pairing
in the context of the I2S interface.
- Enhanced to include instruction families and layouts, improving the APU formats and circuit validation.
- Introduced for handling binary layouts derived from C structures.
- Added to manage APU instruction families and ensure opcode integrity.
- Updated to track global presentation changes, specifically repository footer modifications.
- Created to resolve architectural storage geometry and validate storage configurations.
- Implemented comprehensive tests in and to ensure correctness of diagram coverage and storage geometry.
maksyuki