Implement the memory replacement required by chapter 3 of the OpenC906
integration manual for the Mini HP core. The eight aq_spsram_* single-port
SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag)
gain reviewed overrides in rtl/mini/ip_overrides/, registered in
scripts/generate_openc906.py with sha256 pins on the vendored files at the
locked revision b0c06eb1.
Each override keeps the upstream behavioral aq_f_spsram_* instance
byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without
PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual
section 3.1.5 (depth stacks with a read-registered bank select, width
stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN
onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off,
matching the tc_sram.sv convention. Committed CI profiles keep
PDK_BEHAV=YES, so their simulation results are unchanged.
The Makefile also lists the new overrides as prerequisites of the
generated-filelist stamp so editing one forces regeneration.
Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus)
and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on
the macro path.
The Mini HP core is the locked OpenC906 with T-Head XTheadCmo custom-0
dcache maintenance; the former rv64imafdc_zicbom_max VexiiRiscv
configuration survives only as the frozen Std-series generator asset.
Sweep the leftover wording:
- scripts/README.md gains the missing setup_openc906.py and
generate_openc906.py entries (locked source install; sha256-pinned
overrides; single compilation unit below build/).
- configs/README.md and app/README.md describe the OpenC906 core and
XTheadCmo maintenance instead of VexiiRiscv RTL generation and Zicbom.
- The npu-p5-hp-sim help line and the npu_p5_report.py emitted HP
evidence mode now say polling-xtheadcmo, matching the payload's
actual dcache.cva/iva mechanism.
- Adjusted slot assignments in to reflect new peripheral mappings.
- Updated to validate new OpenC906 configurations, including generator and profile checks.
- Modified to reference the new Std-series VexiiRiscv generator.
- Changed cache maintenance instructions in to align with C906 specifications.
- Revised assertions in to account for internal unit removals.
- Updated to reflect changes in peripheral interface counts and policies.
- Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
- Implemented tests for WS2812 DMA sessions and refill functionality in .
- Added a new RTL testbench for WS2812 refill functionality in .
- Enhanced AXI4 data crossbar testbench to diagnose MMIO boundaries for the Mini DMA.
- Created a new Python test suite for Tiny R2 P3 to validate firmware warnings and layout placements.
- Updated existing WS2812 tests to parameterize and check for DMA backpressure integration.
- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced for deterministic corpus framing, CRC checks, and regression evidence for NPU-P6.
- Added to validate NPU-P6 reference execution.
- Created a new RTL model for gate-level NPU transactions.
- Updated to instantiate and streamline the testbench.
- Enhanced with capability checks and added NPU-P6 reference contract tests.
- Modified to include in the source list and refactor rejection logic.
- Updated README.md to document new test scripts and their purposes.
- Introduced differential tests for the APU-P7 frontend profile-1 BAM to ensure consistency with ROM and generator outputs.
- Implemented concurrent decode and continuous KWS smoke tests for APU-P7 to validate system stability under load.
- Added accuracy qualification tests for APU-P7 to verify through-hardware performance against expected results.
- Created contention tests for APU-P8 to assess USB2/SDIO0/APU Gateway A interactions.
- Developed quiesced loader admission tests for APU-P8 to ensure proper handling of DMA operations.
- Added post-fault visibility tests for APU-P8 HP interconnect to confirm fault handling capabilities.
- Enhanced register parity tests to include ABI digest verification for consistency across implementations.
- Updated publication register tests to reflect changes in capability constants for P5 and P7 profiles.
- Removed unsupported fault handling from and replaced it with a test for average pooling execution.
- Updated the test for unsupported placements to validate average pooling and depthwise convolution placements.
- Introduced new tests for softmax functionality in , including parameter validation and edge cases.
- Added qualification tests to ensure rejection of common-mode numerical errors and incomplete runs in .
- Enhanced RTL tests to cover memory downsizing and kernel burst capabilities in and .
- Adjusted boot status assertions in to reflect updated expected values.
- Added validation checks for GA2D soft reset and error handling in .
- Improved resource controller tests in to cover IRQ routing and ownership scenarios.
- Updated performance log tests in to reflect changes in GA2D features and formats.
- Introduced a new netlist transaction test for GA2D in to ensure synthesized block functionality.
- Modified publication software tests in to account for new GA2D stages.
- Adjusted script tools tests in for updated configuration values.
- Added print statements for better traceability in GA2D reference campaign tests.
This commit introduces a comprehensive set of unit tests for the NPU-P3 job execution, covering the DMA engine, job decoder, and core functionalities. The tests utilize Icarus and Verilator for simulation and include descriptor validation, fault handling, and various operational scenarios. Key features include:
- Descriptor construction and validation mirroring ABI 1.0.
- Detailed test cases for valid and invalid descriptors.
- Core testbench scenarios for various operations including convolution, pooling, and fully connected layers.
- Integration of golden model comparisons for output verification.
These tests aim to ensure robust functionality and adherence to specifications for the NPU-P3 architecture.
- Introduced to ensure consistency between RTL and C register definitions.
- Implemented exhaustive checks for offsets, scalar encodings, bit shifts, and enumerations.
- Added for shell and control-CDC unit tests using Icarus and Verilator.
- Created test cases for NPU register and control CDC functionality, verifying successful simulation outputs.
- Introduced for comprehensive testing of the NPU vector module, covering bias preload, lane-masked accumulation, and fault conditions.
- Created to implement differential tests for NPU compute-core RTL using Icarus Verilog and Verilator, ensuring bit-exact results against a numerical oracle.
- Added to validate NPU memory and patch packer functionality, including SRAM models and various packing scenarios.
- Introduced to validate KWS and VWW locked model graphs against expected configurations, including operator sequences, tensor properties, and model integrity checks.
- Added to cover numerical profiles and validate arithmetic operations, including convolution, depthwise convolution, fully connected layers, and various tensor operations.
- Created to ensure proper setup and validation of NPU-P0 reference flow, including dataset integrity and model hash consistency.
- Implemented error handling tests for malformed buffers and model mutations to ensure robustness.
- Adjusted the native JPEG path to reflect one normal read and one normal write credit for master slot 6 in various documentation files, including README.md, datasheets, and programming references.
- Updated the bus programming section to clarify the admission policy and error handling for the JPEG private path.
- Enhanced the media formats and product use sections to specify the implications of the new credit structure on system integration and performance.
- Modified the RTL implementation to ensure proper credit allocation for the JPEG master in the AXI4 data crossbar.
- Updated regression tests to validate the new credit handling and ensure compliance with the updated specifications.
- Increased simulation timeout for Verilator to accommodate new testing requirements.
- Updated resource_controller_tb.sv to verify resource STATUS bit layout after HP handoff.
- Modified test_ga2d.py to reflect changes for GA2D Phase 4, including memory map generation and source file handling.
- Introduced new test_ga2d_dma.py for independent FILL/COPY reference-model coverage.
- Updated test_ga2d_platform.py to check for the activation of the private AXI64 master and IRQ routing.
- Adjusted test_ga2d_register_parity.py to validate new scalar encodings for Phase 4.
- Enhanced test_hp_boot_bundle.py to ensure HP boot uses the private GA2D mailbox and resource lifecycle.
- Updated test_hp_platform.py to verify GA2D lifecycle markers and cache handshake budget.
- Modified test_performance_log.py to include GA2D workload and configuration facts in performance logs.
- Adjusted test_publication_retrieval.py and test_publication_software.py to reflect changes in GA2D stages.
- Updated test_script_tools.py to ensure GA2D formal filelists are correctly scoped.
- Refactored test_soc_topology.py to validate the private master policy and active shell in GA2D Phase 4.
- Updated resource_controller_tb.sv to include additional checks for IRQ handling and lifecycle states for GA2D resource.
- Modified soc_irq_topology_tb.sv to accommodate 64-bit IRQ vector handling and updated expectations for IRQ routing.
- Introduced test_ga2d.py for directed verification of GA2D Phase 3 APB4 shell functionality.
- Revised test_ga2d_platform.py to reflect changes in GA2D integration and ensure proper IRQ routing.
- Added test_ga2d_register_parity.py to synchronize GA2D RTL and SDK register constants.
- Updated test_lp_irq.py to reflect changes in IRQ allocation and metadata for GA2D.
- Enhanced test_memory_map.py to verify GA2D MMIO region presence in the memory map.
- Adjusted test_publication_software.py to include GA2D in application results.
- Modified test_soc_topology.py to ensure correct topology generation for GA2D, including IRQ and APB bindings.
- Updated onchip_ram64_tb to increase ID_WIDTH from 6 to 7 and adjusted related write/read tasks.
- Modified resource_controller_tb to accommodate an expanded resource count from 8 to 9, updating related logic signals.
- Enhanced sysctrl_tb to introduce new fault handling logic for data plane faults, including additional fault validation and delivery mechanisms.
- Added tests for clock and reset domains to ensure proper handling of data plane faults and their reset contracts.
- Introduced new test_ga2d_platform.py to verify GA2D Phase 2 functionality, including lifecycle and recovery processes.
- Updated test_soc_topology.py to ensure proper data master policies and validate GA2D integration within the system.
- Enhanced sysctrl.py to ensure the fault master retains the high bit for data plane faults.
- Implemented the KWS engine in the RTL and added necessary components including KWS SRAM client and model loader.
- Enhanced the APU ring scheduler testbench to validate KWS descriptors.
- Introduced new Python tests for KWS functionality, including model import validation, inference checks, and error handling for mutated models.
- Updated existing tests to include KWS components and ensure proper integration within the APU architecture.
- Refactored code for clarity and consistency, including adjustments to signal handling and memory management in test cases.
- Added new tests for FLAC encoding and decoding, including handling of rice parameters and partial LPC tail.
- Introduced WAV PCM encoding tests to ensure correct behavior across various configurations.
- Updated test cases to validate the handling of malformed FLAC files and metadata structures.
- Enhanced the APU register tests to include expanded P5 profile capabilities and ensure accurate register descriptions.
- Improved assertions for manifest checks in the APU release tests to validate ABI and instruction counts.
- Refactored existing tests for clarity and maintainability, ensuring they align with the latest APU specifications.
- Modified the capability register value in apu_reg_tb.sv to 0x01bd.
- Simplified rejected write checks for the COMMAND register in apu_reg_tb.sv.
- Added backend build ID input to the ring scheduler testbench.
- Updated test cases in test_apu.py to include new codec transport and controller files.
- Created new test file test_apu_codec_transport.py for APU-P5 transport assembler and parser tests.
- Added codec profile and dependency tests in test_apu_codecs.py.
- Enhanced register parity tests to include P5 primitive mask.
- Improved script tools tests for file download functionality and dependency helpers.
maksyuki