- Updated RTL style audit to reflect new APB4 naming conventions.
- Changed performance log parsing to accommodate new APB4 wait signals.
- Modified AXI4 interconnect and rib bus testbenches to use updated performance wait signals.
- Adjusted IRQ topology testbench to use new APB4 peripheral and system IRQ widths.
- Updated sysctrl testbench to reflect changes in APB4 performance wait signals.
- Refined memory map tests to check for new APB4 definitions.
- Enhanced performance log tests to validate new APB4 wait signal parsing.
- Revised SOC topology tests to ensure correct APB4 peripheral and system bindings.
- Updated user extensions tests to align with new APB4 interface naming.
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface.
- Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files.
- Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests.
- Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
maksyuki