- Updated to integrate a coefficient engine and additional signals for coefficient handling.
- Modified to include a coefficient engine, enhancing the encoding process with new signals.
- Improved to validate generated blocks against expected values and added timeout handling.
- Introduced for testing SRAM wrappers in JPEG workspace.
- Enhanced test coverage in to reject invalid STA net drivers.
- Updated to ensure proper coverage of canonical domains in timing contracts.
- Added a new test for JPEG coefficient engine in .
- Improved memory map tests in to validate public active MMIO regions.
- Enhanced management core specification tests in to verify high-performance core specifications.
- Added behavioral-only checks in to exclude synthesis and netlist consumers.
- Updated SDRAM tests in to track active firmware memory.
- Enhanced STA constraints tests in to cover current clock domains and net drivers.
- Introduced to validate AXI4 interface for 64-bit on-chip SRAM.
- Added to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated to include resource controller interface.
- Enhanced to cover additional IRQ scenarios.
- Added new tests in for AXI4 target guard timeout and isolation.
- Updated to reflect changes in the high-performance profile.
- Modified to verify on-chip SRAM bank configurations.
- Added for directed verification of resource controller.
- Updated to check SDRAM mapped window coverage.
- Enhanced to ensure correct IRQ mappings and APB target generation.
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios.
- Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling.
- Introduced clock frequency monitor tests to ensure detection of clock stop and restart events.
- Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling.
- Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities.
- Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Added TCD head and count registers to DMA definition and register files.
- Introduced CRC expected and result registers for enhanced error checking.
- Updated DMA version to 2.0 to reflect new features.
- Modified DMA testbench to validate new TCD and CRC functionalities.
- Enhanced README and filelists to include new dependencies and configurations.
- Updated formal verification and runtime tests to accommodate new DMA features.
- Introduced to handle the preparation of the SKY130 OpenRAM SRAM views.
- Updated to download and prepare the SRAM archive during PDK setup.
- Enhanced OpenSTA and Yosys configurations to accommodate SRAM macro integration.
- Added Verilog simulation models for GF180 and SKY130 SRAM macros.
- Implemented tests for SRAM setup and validation, ensuring correct integration and functionality.
- Updated various Makefiles and scripts to support SRAM size and macro configurations.
- Updated filelist to include sg13g2_udp.v for IHP130.
- Modified sdram_axi4.sv to initialize read and write control signals.
- Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad.
- Updated iverilog.mk to support IHP130 in tech-cell-test.
- Enhanced pin_map generation to include power pads for IHP130.
- Updated tc_io modules to handle power pins for IHP130.
- Added timing contract generation in package.py for commercial flow.
- Enhanced test cases to validate new IHP130 features and configurations.
- Added new tests for LibreLane flow specific to IHP130.
- Introduced and for STA flow, enabling scenario loading and timing analysis.
- Added for synthesis flow, defining the synthesis process and generating reports.
- Implemented for synthesis, including library handling and design checks.
- Enhanced to support additional filelists and include directories for SOC export.
- Added ICS55 PLL implementation in with corresponding testbench .
- Created comprehensive tests in for various flow components and scenarios.
- Updated to forward new filelist arguments for SOC generation.
- Improved to validate source export functionality and ensure proper file handling.
- Deleted references to XEZIM and CVC in the Makefile and related scripts.
- Removed XEZIM-specific and CVC-specific files, including external memory models and SRAM models.
- Updated the test suite to reflect the removal of XEZIM and CVC simulators, ensuring no broken references remain.
- Cleaned up the README and doctor scripts to remove mentions of XEZIM and CVC.
- Updated README.md to clarify the status of KianV RV32IMA and PicoRV32 in the user-extension map.
- Modified Makefile to include USER_EXTENSIONS_SOURCE in MPW variant stamp dependencies.
- Enhanced integration README.md to better describe the relationship between user_extensions.json and mpw.toml.
- Updated generate_user_extensions.py to include design_id in ExtensionTarget and enforce unique design IDs.
- Changed user_extensions.json schema version to 2 and added design_id fields for core and IP targets.
- Refactored generate_mpw.py to support the new manifest structure and validate design selections.
- Adjusted sysctrl_tb.sv test cases to reflect changes in user core reset states.
- Enhanced test_opipsram.py to utilize ccache for improved compilation performance.
- Updated test_script_tools.py to include new tests for active manifest generation.
- Modified test_user_extensions.py to validate isolated scalar bindings and reject duplicate design selections.
- Updated memory map tests to include OPI PSRAM address and size definitions.
- Introduced new test suite for OPI PSRAM to ensure RTL and HAL ABI consistency.
- Enhanced script tools tests to validate formal filelists for OPI PSRAM.
- Modified SOC topology tests to incorporate OPI PSRAM bindings and IRQ mappings.
- Introduced burst length handling in the SDRAM Verilator model, allowing for more flexible read/write operations.
- Added new SDRAM-related source files to the project structure, including sdram_pkg.sv and sdram_axi4.sv.
- Updated software makefile to include new SDRAM-related C source files for HAL.
- Enhanced C test suite with new tests for SDRAM timing and functionality, ensuring proper integration with the HAL.
- Improved RTL testbench for SDRAM, adding support for burst writes and reads, and verifying data integrity.
- Updated Python test scripts to reflect changes in SDRAM handling and ensure comprehensive coverage of SDRAM functionality.
- Added checks to ensure register offsets between RTL and HAL definitions match, maintaining consistency across the codebase.
- Introduced SYNTH_RECIPE variable to select between balanced, area, and speed synthesis recipes.
- Updated Makefile to handle new SYNTH_RECIPE variable and its validation.
- Modified synthesis scripts to utilize the selected recipe, ensuring outputs are directed to the appropriate directories.
- Enhanced documentation to reflect changes in synthesis flow and directory structure.
- Added tests to verify correct behavior of new synthesis recipes and their integration into the regression suite.
- Removed obsolete scripts and configurations related to previous synthesis methods.
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface.
- Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files.
- Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests.
- Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
- Introduced sysctrl_define.svh to define register offsets and constants for SysCtrl.
- Created sysctrl_if.sv interface for communication with SysCtrl.
- Implemented sysctrl_reg.sv module to handle register read/write operations and state management.
- Developed sysctrl_tb.sv testbench to validate SysCtrl functionality, including lifecycle, fault handling, performance monitoring, and RTC wake status.
- Added Python regression test (test_sysctrl.py) to automate SysCtrl verification using Icarus Verilog.
- Enhanced the RTL style checker script to include new diagnostic rules for function declarations, primary design units, and synthesis exclusions.
- Added functions to handle audit issues, ensuring that the audit records match the current inventory of RTL files.
- Updated test cases to reflect changes in RTL file names and paths, ensuring consistency with the new naming conventions.
- Introduced additional tests for style violations, including mismatched primary design units and synthesizable initial blocks.
- Adjusted file paths in various test files to align with the new RTL structure and naming conventions.
- Introduced common setup script for Yosys () to manage global variables and configurations.
- Added output filtering script () to enhance log readability.
- Created technology initialization script () for handling different PDKs.
- Developed main synthesis script () to orchestrate the synthesis flow using Yosys.
- Added a configuration makefile () for synthesis settings.
- Updated Yosys makefile () to integrate new scripts and configurations.
- Adjusted paths in and RTL filelists to reflect new directory structure under .
- Modified various scripts and test files to accommodate the new PDK paths and ensure compatibility.
- Enhanced warning normalization in the analysis script to preserve PDK signatures.
- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure.
- Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency.
- Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure.
- Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors.
- Updated and to reflect changes in bus naming conventions.
- Enhanced to include AXI4-Stream interface checks and validate stream data transfers.
- Modified to integrate AXI4-Stream interfaces for improved DMA testing.
- Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification.
- Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation.
- Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
- Updated Makefile to include a check for the RNG metadata script and added a dependency for it.
- Modified memory_map.json to change the user access level of APB_RNG to 'none'.
- Updated clusterip filelist to include new RNG source files.
- Adjusted generate_soc_topology.py to replace the reserved IRQ with the RNG IRQ.
- Updated soc_topology.json to reflect the new RNG interrupt configuration.
- Added RNG source files to software.mk for compilation.
- Enhanced ip_apb_wrapper.sv to instantiate the RNG core and connect it to the APB interface.
- Updated test_memory_map.py to ensure SOC_ADDR_IS_APB_RNG is not defined.
- Modified test_script_tools.py to ensure dry runs do not write filelists.
- Updated test_soc_topology.py to verify the new RNG IRQ and adjust the user IRQ mask.
- Introduced scripts and makefile targets for generating architecture information metadata.
- Updated the filelist generation to include archinfo metadata files.
- Modified software.mk to include archinfo source files and headers.
- Enhanced the ip_apb_wrapper and user_ip_wrapper to integrate archinfo components.
- Updated tests to ensure stability and correct path expansions for generated files.
- Removed unnecessary files from the clusterip filelist.
- Updated to include I2C1 in IRQ bindings.
- Modified to increase IRQ group width and add I2C1 interrupt.
- Enhanced to include I2C formal properties and adjust timeouts.
- Added I2C-related source files to the formal verification flow.
- Updated DMA wrapper in to handle I2C DMA signals.
- Created a new testbench for I2C functionality verification.
- Implemented I2C helper functions in for testing.
- Added I2C tests in to validate controller behavior and recovery.
- Updated existing tests to accommodate changes in DMA and IRQ handling.
- Updated to include for testing.
- Modified to include GPIO header and added tests for GPIO functionality.
- Created a new testbench for GPIO V2, covering register and pad-control contracts.
- Removed obsolete and its associated test.
- Updated to include GPIO admin base routing.
- Added a new Python test for GPIO V2 register and pad-control contract.
- Removed as its functionality is now covered in .
- Updated memory map tests to ensure GPIO admin base is correctly referenced.
- Adjusted formal filelist generation to reflect changes in GPIO handling.
- Enhanced SOC topology tests to include GPIO interrupt handling.
- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.
- Replace onewire interface with ws2812 interface in retrosoc module.
- Include ws2812_math.c in C test sources.
- Add ws2812 header in test_runtime.c and implement ws2812 helper tests.
- Update ribp_topology_tb and soc_irq_topology_tb to handle ws2812 interface.
- Create ws2812_dma_tb and ws2812_tb for testing WS2812 DMA and waveform functionality.
- Enhance test_script_tools.py to include ws2812 in formal filelists.
- Modify test_soc_topology.py to ensure proper IRQ mapping for ws2812.
- Introduce test_ws2812.py for WS2812 register, waveform, and streaming regression tests.
- Introduced test status signals (test_done_o, test_pass_o, test_code_o) in sysctrl interface and module.
- Updated memory map to include TEST_STATUS offset.
- Enhanced retrosoc_tb to monitor test completion and report results.
- Modified Emulator to handle test status and return appropriate exit codes.
- Updated formal verification to include assertions for test status.
- Added CoreMark log parsing script and integrated it into the regression tests.
- Implemented tests for test status handling in sysctrl_fault_tb.
- Adjusted simulation success and failure markers in various scripts and tests.
- Ensured compatibility with existing performance logging and regression testing frameworks.
- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files.
- Updated the Emulator class to remove JTAG-related debug signals and configurations.
- Adjusted the pin map and JSON configurations to exclude debug-related entries.
- Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core.
- Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions.
- Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.
- Implemented module to handle debug reset requests, ensuring proper synchronization with the AHB-Lite bridge.
- Created to integrate JTAG-DTM and Debug Module, facilitating abstract command exposure.
- Updated and modules to include JTAG interface signals.
- Enhanced the development environment with scripts for running debug sessions using OpenOCD and GDB.
- Added tests for management debug reset functionality and JTAG integration, ensuring correct behavior under various scenarios.
- Updated SDC generation to include JTAG clock domain and port requirements.
- Modified various scripts to support new debug features and ensure compatibility with the Hazard3 architecture.
- Added .dockerignore to exclude unnecessary files from Docker context.
- Updated Makefile to include a new setup-regression target for installing dependencies for all PR PDK profiles.
- Enhanced README with installation instructions for Docker and Nix environments.
- Created Dockerfile for a lock-pinned Ubuntu 22.04 development image.
- Added entrypoint script for Docker container to set up the environment.
- Introduced flake.lock and flake.nix for Nix package management.
- Updated dependency_lock.py to validate Nix inputs and container images in the lock file.
- Implemented development_environment.py for managing the development environment setup.
- Enhanced package.py to include container components in the SBOM.
- Added tests to ensure the development environment contract is lock-pinned and validate container and Nix environment files.
- Changed the interface from ribp to rib in soc_topology.json and related files.
- Updated formal.mk to reflect the new rib2apb naming convention.
- Implemented rib2apb module to handle RIB to APB communication.
- Modified bus.sv to integrate the new rib2apb module and adjust signal assignments accordingly.
- Updated testbench files to use the new rib interface and validate the RIB to APB functionality.
- Created rib2apb_tb for testing the direct RIB to APB bridge.
- Adjusted script tools and test scripts to accommodate the new naming and structure.
- Renamed and to and respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench to validate RIB to RAM interactions.
- Created for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
- Introduced to define formal properties for the sysctrl module.
- Updated to include new formal properties and source files.
- Renamed to in the bus module and created a new file.
- Implemented a testbench for in .
- Removed the obsolete test file.
- Updated test scripts to reference the new instead of the old RAM module.
- Adjusted various test files to ensure compatibility with the new structure and naming conventions.
- Updated test cases in , , , , , , , and to replace references from RIB to RIBP.
- Modified file names and paths in tests to align with the new RIBP naming conventions.
- Ensured that all assertions and checks in the tests are consistent with the updated RIBP interfaces and functionality.
- Added a new test for migrating user core RIBP interfaces in .
- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers.
- Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance.
- Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands.
- Created spill_register_tb to verify the functionality of the spill register under various conditions.
- Modified test_dma.py to reflect changes in DMA error handling and performance reporting.
- Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities.
- Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior.
- Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces.
- Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py.
- Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface.
- Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors.
- Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
- Updated NMI interface references from to in multiple files for consistency.
- Added a new script to convert UART performance records into structured JSON format.
- Enhanced the README documentation to include details about the new performance log parser.
- Implemented tests for the new performance log parser to ensure correct functionality.
- Added new test cases for DMA error handling and SDRAM data integrity to improve coverage.
- Updated existing test cases to accommodate changes in the NMI interface and added performance metrics.
- Refactored bus fault testbench to include fault code checks and improved error handling.
- Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.
- Introduced Verilator and Yosys warning configurations for ICS55.
- Updated RTL filelists to include functional models for ICS55.
- Modified memory modules to use wire instead of logic for clock and reset signals.
- Enhanced Makefile and Iverilog configurations to support ICS55.
- Implemented new simulation cells for ICS55 in the tech library.
- Updated regression scripts and tests to include ICS55 support.
- Added functionality to prepare ICS55 liberty and simulation models.
- Enhanced testbench to validate ICS55 specific components and behaviors.
maksyuki