1045 Commits

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Author	SHA1	Message	Date
maksyuki	118051a764	feat: modify tinylcd driver impl	2025-02-22 14:04:01 +08:00
maksyuki	7bbac48994	feat: add pll timing constr sdc	2025-02-21 12:27:05 +08:00
maksyuki	ad03fd6921	docs: modify max freq comment in the psram core	2025-02-21 11:08:48 +08:00
maksyuki	a35573ea56	feat: add schmitt reg to the gpio	2025-02-20 21:05:56 +08:00
maksyuki	23d0c5584c	chore: modify simv ignore rule	2025-02-20 15:26:42 +08:00
maksyuki	173eb47d32	chore: modify daidir ignore rule	2025-02-20 14:53:24 +08:00
maksyuki	185507329e	fix: fix a typos in net sim target	2025-02-20 14:52:29 +08:00
maksyuki	64da1209fd	chore: rm unused IPs	2025-02-20 14:51:45 +08:00
maksyuki	2290535f57	feat: add syn vcs flag into the tb file	2025-02-20 14:43:44 +08:00
maksyuki	30248ba920	feat: add net sim comp and sim target	2025-02-20 14:39:43 +08:00
maksyuki	72efb941b4	chore: modify verdi dynamic lib addr	2025-02-20 10:35:00 +08:00
maksyuki	e42f56a668	feat: add psram more perf tuning for tht 144MHz	2025-02-19 12:32:06 +08:00
maksyuki	a571ce69c3	feat: split all app into different files	2025-02-19 12:02:22 +08:00
maksyuki	7af0a0b802	feat: add more boot cnt up limit to meet 133MHz	2025-02-18 23:00:17 +08:00
maksyuki	7d6a4a6ebc	feat: add psram mem test	2025-02-18 22:53:00 +08:00
maksyuki	2f90681eed	feat: improve timing paras to support 133MHz	2025-02-18 16:50:56 +08:00
maksyuki	134d149533	fix: fix the high 8bits of rd oper	2025-02-18 15:35:35 +08:00
maksyuki	76276088b4	feat: adjust the extern chd cycles to max 3	2025-02-18 10:43:26 +08:00
maksyuki	4984f352b5	feat: add extern cycle for meeting the tCHD when sclk is max 84HHz	2025-02-18 10:00:00 +08:00
maksyuki	c03c76ac89	fix: adjust the rd xfer data pos	2025-02-17 17:31:45 +08:00
maksyuki	3545dcd970	feat: add rd ctrl logic	2025-02-17 16:58:21 +08:00
maksyuki	57041e8a07	feat: modify rd oper order and some code styles	2025-02-17 16:29:35 +08:00
maksyuki	a9bce953e3	feat: split one byte to send	2025-02-17 16:02:19 +08:00
maksyuki	46ebf141a0	fix: fix wrong wr byte order	2025-02-17 14:23:36 +08:00
maksyuki	662148d3b9	chore: rm unused spaces in fpga sdc contr file	2025-02-17 12:02:19 +08:00
maksyuki	2d0256c2f0	fix: fix wrong byte order issue	2025-02-17 12:00:33 +08:00
maksyuki	bcff2ac78b	fix: fix rdata error radix select	2025-02-17 11:28:34 +08:00
maksyuki	bc1688dd17	fix: add rd mask to the rd data in psram	2025-02-17 10:50:11 +08:00
maksyuki	2e48aa647f	fix: fix a typos on psram mosi and miso pin wire pos	2025-02-17 09:05:45 +08:00
maksyuki	b1ee4705fa	feat: replace the io0 and io1 pin constr	2025-02-16 23:41:56 +08:00
maksyuki	4923cb1ffb	fix: fix rd cnt up limit value	2025-02-16 20:34:15 +08:00
maksyuki	0aecc9efa4	fix: fix rd bit cnt set error	2025-02-16 19:04:26 +08:00
maksyuki	58ff55e543	feat: rm unsed psram ce signals	2025-02-16 18:36:56 +08:00
maksyuki	e51d332b4d	fix: fix byte xfer cnt error	2025-02-16 18:18:09 +08:00
maksyuki	df178830b7	fix: add init xfer wr data left shift	2025-02-16 17:16:59 +08:00
maksyuki	651fc0ee20	fix: fix xfer data wrong data width	2025-02-16 16:43:27 +08:00
maksyuki	edcd462024	feat: modify cmd psram rd/wr test oper	2025-02-16 15:48:53 +08:00
maksyuki	06d9a9ad65	chore: add '&' to the verdi cmd	2025-02-16 15:35:00 +08:00
maksyuki	40e94f696f	chore: add psram core to the make and yosys script	2025-02-16 15:28:10 +08:00
maksyuki	00daeb2605	feat: rewrite the psram module	2025-02-16 15:27:10 +08:00
maksyuki	7d49b8ce9c	feat: add xfer ctrl logic	2025-02-15 20:39:18 +08:00
maksyuki	ea21aa9da7	fix: add hard codes to debug the mem bus	2025-02-15 19:37:59 +08:00
maksyuki	1a826ef54d	fix: fix psram wrong addr input	2025-02-15 19:26:30 +08:00
maksyuki	4433c07405	fix: fix a rst init value bug	2025-02-15 17:42:12 +08:00
maksyuki	f11ca7df45	feat: rewrite the psram module	2025-02-15 17:37:47 +08:00
maksyuki	41c6dd1b80	fix: fix pll up limit factor	2025-02-14 14:19:19 +08:00
maksyuki	bc84288b51	fix: split pll switch and bp func	2025-02-14 13:57:56 +08:00
maksyuki	116d2e5a73	feat: add div4 to the spfs clk div	2025-02-14 13:49:40 +08:00
maksyuki	bd21f792d9	fix: fix pllen output logic	2025-02-14 11:28:59 +08:00
maksyuki	89cc8c3497	fix: fix no clk bypass pll config bp mode	2025-02-14 11:20:11 +08:00