Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md
adds the tiling table (8-bit macro stacking with registered read muxes),
notes the repo-owned functional models versus the vendor collateral in the
locked PDK, and documents the SKY130 byte-mask blocker as the reason that
PDK stays behavioral; hp-rv64-validation.md records the directed-TB,
MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs
generalize the override wording to IHP130/ICS55/GF180. Physical
qualification (Liberty registration, STA, LEC) stays explicitly deferred.
The gf180 boot testbench mode defines PDK_GF180 and therefore now compiles
the SRAM macro branches alongside the ICG cells: add the repo-owned
gf180_sram_sim_cells.sv to its model list and rename the test to
test_c906_boots_smoke_payload_with_gf180_macros. Both GF180 models are
repo-owned, so the mode no longer depends on the PDK checkout.
Evidence: tests/test_hp_platform.py passes 20/20 with all five boot modes
(behavioral, ihp130, ics55, sky130-icg, gf180); the CI-flavored gf180
profile simulation passes at 26,462,456 cycles with SIM_TEST_PASS code=0.
Add a PDK_GF180+HAVE_SRAM_MACRO (without PDK_BEHAV) branch to each of the
eight aq_spsram_* overrides, tiling the 8-bit GF180 macros
(sram{64,128,256,512}x8m8wm1, per-bit active-low WEN, matching polarity so
no inversion is needed): 512x8 tiles with registered read-mux depth
stacking for 1024x16/2048x32/1024x64, width stacks of depth-exact 256x8
and 64x8 tiles for 256x59/64x58/64x88/64x98 (partial top tiles tie unused
WEN bits inactive), and a single exact 128x8 tile for the dirty array.
VDD/VSS follow the tc_sram.sv GF180 convention.
The GF180 CI profile (HAVE_HP=YES, HAVE_SRAM_MACRO=YES, PDK_BEHAV unset)
now compiles the macro path automatically. Behavioral, IHP130, and ICS55
paths are bit-identical. SKY130 intentionally stays behavioral: the locked
OpenRAM macro offers only byte-granular wmask0 while six of the eight C906
arrays require per-bit writes (BHT one-hot, 29/44/48-bit field groups,
single-bit dirty updates).
Evidence: directed 8-wrapper equivalence TB and the MEM_INTF adaptation
pass on the GF180 path; the gf180 boot testbench and the GF180 SoC
hp-smoke-sim both pass (SIM_TEST_PASS code=0, 3,644,186 cycles, identical
to every other macro mode).
Extend gf180_sram_sim_cells.sv with pin-compatible functional models for
gf180mcu_fd_ip_sram__sram{64,128,256}x8m8wm1, matching the existing 512x8
model's style and behavior (registered read, per-bit active-low WEN,
VDD/VSS sanity checks). All four geometries ship vendor collateral in the
locked gf180mcu-pdk checkout; the repo-owned models keep simulation
self-contained per the existing convention. No filelist change: the file
is already listed in pdk_gf180.fl.
Close out the chapter 3 documentation: hp-platform.md gains the ICG
section (three override points, per-PDK cell table, the ICS55 SE-into-E
note, and the two-state reset rationale), leaving only physical/STA
qualification deferred; hp-rv64-validation.md records the MEM_INTF ICG
results, the five boot testbench modes, and the four SoC-level runs with
the remaining gaps; the two READMEs extend the override inventory to
hart-ID + sysmap + SRAM wrappers + clock-gating cells.
The ihp130/ics55 macro-mode boot testbenches define PDK_IHP130/PDK_ICS55,
so they now also compile the ICG branches: extend their model sets with
sg13g2_udp.v+sg13g2_stdcell.v and ics55_h7cr_functional.v respectively
(the latter with +define+functional, mirroring pdk_ics55.fl). Add
test_c906_boots_smoke_payload_with_sky130_icg and ..._gf180_icg covering
the two PDKs whose SRAM wrappers intentionally stay behavioral (mixed-mode
coverage); both skip when the PDK checkout is not materialized.
Evidence: all five boot testbench modes pass with HP_C906_BOOT_TEST_PASS
(5 passed, 634s); whole-SoC macro+ICG runs pass for IHP130 and ICS55
(hp-smoke-sim, SIM_TEST_PASS code=0 with the GA2D lifecycle markers), and
the CI-flavored sky130/gf180 profile simulations pass at 26.46M cycles.
Complete the integration manual chapter 3 cell swap (the ICG half; the
SRAM half landed earlier). Three new reviewed overrides, registered in
generate_openc906.py with sha256 pins on the vendored files and added to
the generated-filelist stamp prerequisites:
- gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM):
pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/
PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell
(sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E
because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with
SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off).
- BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model
stays byte-identical by default; the same four PDK branches substitute
the process cell with the scan input tied off.
The GF180 branch uses a repo-owned icgtp_1 functional model in
rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent)
because the vendor functional model references a UDP latch primitive that
the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor
sdlclkp model through pdk_sky130.fl, following the existing cell pattern.
ASIC CI profiles with PDK_BEHAV unset now compile real clock gating;
PDK_BEHAV=YES profiles are bit-identical.
Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK
cell paths (Icarus adaptation); the five-mode boot testbench suite passes
on top of this change.
Real clock-gating cells deadlocked the C906 boot in two-state Verilator:
a reset held low from t=0 never fires an async-reset flop's reset branch,
and the DTM sleeps at boot (dmactive=0), so the gated dm_pclk never edges
and dm_core_rstn (reset value 1) kept its zero-init 0, holding the core in
reset forever. Drive pad_yy_icg_scan_en/pad_tdt_icg_scan_en with the
inverted core/APB reset so every gate is transparent while in reset and
async-reset flops initialize on running-clock edges — the standard POR
clock-force pattern silicon gets from the held level.
Pass-through (default/PDK_BEHAV) builds ignore SE entirely; the default
ihp130-hp smoke run stays cycle-identical (3,644,186 cycles), proving the
change is inert until real ICG cells are compiled in.
Extend the chapter 3 SRAM swap documentation to the ICS55 exact-geometry
macros: hp-platform.md describes the direct-replacement mapping and
gating next to the IHP130 stacking table, hp-rv64-validation.md records
the ICS55 boot-TB, MEM_INTF, and SoC macro-sim evidence along with the
precise remaining gaps (Yosys smoke synth needs Liberty registration for
the new macros; STA/LEC stay deferred), and the two READMEs generalize
the override wording to the PDK-selectable IHP130/ICS55 paths.
Generalize the focused boot testbench helper from a boolean to a macro
mode selector (behavioral / ihp130 / ics55) and add
test_c906_boots_smoke_payload_with_ics55_sram_macros, which runs the same
real smoke payload with +define+PDK_ICS55/+HAVE_SRAM_MACRO and the eight
materialized ics55_ecos_sram_* core models; the test skips when the
macros are not materialized. The ICS55 models need no FUNCTIONAL define.
Evidence: all three boot testbench modes pass with
HP_C906_BOOT_TEST_PASS; a whole-SoC macro-mode run via
'make CONFIG=configs/ci/ihp130-hp.mk PDK=ICS55 PDK_BEHAV=NO SIMU=VERILATOR
hp-smoke-sim' passes with SIM_TEST_PASS code=0 and the GA2D cache
lifecycle markers.
Extend each of the eight aq_spsram_* overrides with a
PDK_ICS55+HAVE_SRAM_MACRO (without PDK_BEHAV) branch that instantiates
the matching exact-geometry ics55_ecos_sram_* macro. The ICS55 interface
polarity (CEB/GWEB/WEB active-low, per-bit WEB) matches the wrappers
exactly, so the branch is a single direct instantiation with MARE/MAR
tied off; no inversion, stacking, or padding is needed. Priority order is
PDK_BEHAV behavioral, then IHP130 macros, then ICS55 macros, else the
upstream behavioral model; the behavioral and IHP130 paths are
bit-identical.
The committed ICS55 CI/cluster profiles (HAVE_HP=YES, HAVE_SRAM_MACRO=YES,
PDK_BEHAV unset) now compile the macro path automatically.
Evidence: directed 8-wrapper equivalence TB and the manual section 3.2
MEM_INTF adaptation (Icarus) pass on the ICS55 path; the CI-flavored
ics55 profile simulation passes with SIM_TEST_PASS code=0.
Register the eight exact-geometry OpenECOS ICS55 SRAM macros for the Mini
HP core (1024x16_m8, 2048x32_m8, 256x59_m4, 1024x64_m8, 128x8_m8,
64x58_m4, 64x88_m4, 64x98_m4) as locked archives in
dependencies.lock.json, each pinned to its GitHub release URL and tarball
SHA-256. Extend the setup.py materialization list so 'make setup-pdk'
downloads and extracts them below .cache/retrosoc/pdk/ics55/sram/, and
list the new core models in the ICS55 Icarus/Verilator filelists (stub
entries in the Yosys filelist for cross-file consistency; the synthesis
macro binding itself remains Liberty-side physical collateral).
Evidence: dependency_lock.py validates the updated lock; setup-pdk
materializes all eight macros with verified checksums.
Document the RCU ownership, profile/PDK mapping, exact validation commands,
matched firmware, source snapshots and current 06-00 backend evidence.
Separate historical checkpoints and the rejected 04-00 candidate from
current response-conservation and source-reset validation.
State the production DMA drain and common XPI reset preconditions without
claiming unrestricted standalone bridge source-reset support. Record the
54-case directed result, expected-negative checks and unchanged design
inputs that justify retaining the original backend evidence.
Preserve full-suite failures and focused corrections, interrupted Icarus
attempts, final-phase deferral, negative timing and missing physical
qualification. Keep P7 human acceptance and later phases separate.
Integrate the Tiny RCU, normalized REF24 control, external-input profiles,
single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral
lifecycle control and retained debug behavior. Keep CPU and all 32 main
SRAM macros on SYS and the six private Crypto macros on PCLK.
Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK
operations and focused firmware. Preserve shared-IP defaults and the
ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles.
Use APB/AXI domain bridges and source-owned response holders to preserve
backpressured responses, complete aborted bursts and prevent stale replay.
Verify production DMA source-reset drain and common XPI endpoint reset
with extracted integration bindings and an independent scoreboard.
Add source-bound macro/clock audits, SAFE24 observational STA constraints
and commercial-adapter host checks. No P8 functionality or operating-point
qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md.
Validation: 54 P7 directed tests pass, including both simulators, ten
source-reset ratio runs and two expected-negative drain mutations.
RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs
pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs;
STA remains negative and observational. Source comparison confirms only
the follow-up tests changed after that backend campaign.
Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/
tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility
results and the non-clean full-suite attempt retain their original
attribution. Full Icarus firmware is deferred to final Tiny qualification;
this commit does not constitute human phase acceptance or physical signoff.
Record parent and child process IDs for diagnostics, persist interruption
before cleanup, and ignore repeated termination signals during cleanup.
Close unexpected failures with a terminal result and retain the child's
exit status without treating namespace-local PID absence as completion.
Require a successful terminal run_flow result when checking simulation
logs with an associated result file. Cover repeated cancellation and
reject running, failed or inconsistent terminal records despite PASS text.
This supports the TINY-R2-P7 campaign. Interrupted and timed-out runs remain
non-acceptance evidence; UART output alone cannot qualify a Tiny simulation.
Advance the approved PWM dependency to
38efaf5e20f084a00148920087c60cadab61839b so Tiny RCU can publish the
committed PCLK rate through the existing PWM register interface.
Keep the static-clock default for existing consumers.
Required by TINY-R2-P7 in docs/ip/tiny-soc.md. The locked checkout and
P7 validation use this exact revision; dependency-lock validation passes.
Move the chapter 3 memory swap from deferred to simulation-validated in
docs/ip/hp-platform.md (mechanism, define gating, and the stacking table)
and docs/hp-rv64-validation.md (macro-mode boot TB and SoC macro-sim
evidence, with the remaining synthesis/netlist/STA/LEC gates called out).
Extend the override inventories in rtl/README.md and scripts/README.md to
cover the eight aq_spsram_* wrappers. The chapter 3 ICG replacement and
physical qualification stay explicitly deferred.
Factor the focused hp_core_wrapper boot testbench into a shared helper and
add test_c906_boots_smoke_payload_with_ihp130_sram_macros, which rebuilds
the same real smoke payload run with +define+PDK_IHP130/+HAVE_SRAM_MACRO/
+FUNCTIONAL and the committed RM_IHPSG13_1P_* models. The payload's cache
maintenance and GA2D data movement exercise all eight replaced SRAMs
(BHT/ICache/DCache/JTLB) for real; both modes must reach
HP_C906_BOOT_TEST_PASS.
Evidence: pytest tests/test_hp_platform.py -k boots_smoke_payload passes in
both modes (2 passed); a whole-SoC macro-mode run via
'make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR
hp-smoke-sim' passes with SIM_TEST_PASS code=0 and the
HP_LINUX_READY/HP_GA2D_PASS/HP_GA2D_CACHE_CLEAN markers.
Implement the memory replacement required by chapter 3 of the OpenC906
integration manual for the Mini HP core. The eight aq_spsram_* single-port
SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag)
gain reviewed overrides in rtl/mini/ip_overrides/, registered in
scripts/generate_openc906.py with sha256 pins on the vendored files at the
locked revision b0c06eb1.
Each override keeps the upstream behavioral aq_f_spsram_* instance
byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without
PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual
section 3.1.5 (depth stacks with a read-registered bank select, width
stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN
onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off,
matching the tc_sram.sv convention. Committed CI profiles keep
PDK_BEHAV=YES, so their simulation results are unchanged.
The Makefile also lists the new overrides as prerequisites of the
generated-filelist stamp so editing one forces regeneration.
Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus)
and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on
the macro path.
The C906 ORs the internal CLINT's hardware supervisor-timer line into
mip.STIP (aq_cp0_trap_csr.v: st_int && CLINTEE || stip_reg) and the RTL
resets mxstatus.CLINTEE to 1. Nothing ever programmed STIMECMP, and the
compare registers' 0xFFFF_FFFF reset values are not guaranteed to be
applied (the HP hold-reset produces no async negedge in Verilator, so
the regs stay zero), so st_int fires from the first cycle: the moment
the kernel enables sie.STIE in time_init, it falls into an infinite
supervisor-timer storm and the boot thread starves right after the
sched_clock print. (M-mode firmware is immune, which is why RT-Thread
and OpenSBI were unaffected.)
Probe evidence after the fix: MTIMECMP arms exactly one jiffy out
(mtime+3979 at HZ=250) and MTIP fires exactly at the compare value on a
healthy 288K-cycle cadence; the kernel boots through console init,
BogoMIPS, devtmpfs, and switches to the riscv_clocksource.
Park both compare registers explicitly at cold boot so the state is
deterministic on silicon and in simulation.
Record the shared-IP and eight-channel DMA integration, common I2S/SDIO correctness fixes, deterministic workloads, snapshot update scopes and both PDKs' functional and smoke-flow evidence.
Keep original failed attempts, publication history and source attribution intact. The later final full Pytest passed 1726 tests with one optional pypdf skip in 4021.61 seconds, exit 0, in terminal session 36439; it has no standalone verdict log or JSON. Existing campaign evidence is not rewritten by this documentation commit.
Retain explicit negative timing, warning observations, legacy package/floorplan limits and pending physical qualification. Human phase acceptance and any P7 work remain separate.
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
Document corrected reset behavior, source-bound evidence, validation commands and both PDK timing observations. Mark the earlier reset repair as superseded while preserving its historical attribution.
Retain explicit limits for workload replay, full-function netlist testing and physical qualification. Human phase acceptance and P6 execution remain separate.
Drain remaining write beats before returning B, retain captured R/B responses, and append missing read error beats through the response spills. Preserve first-error attribution and prevent replay after target reset release.
Cover 28 reset scenarios in both simulators, including production DMA drain and APB bridge cases. Extend reset formal checks and publication contract mutation tests.
Validation: 101 focused tests passed; full Pytest reported 1685 passed and one optional pypdf skip. TINY ICS55 and IHP130 PR regressions passed. Timing remains observational and unclosed; no performance or physical qualification is claimed.
Select the HP (OpenC906) JTAG target before the LP releases it, for HP
bring-up debug sessions. Behavior-neutral when off. The knob deliberately
stays out of the variant key: debug runs are not qualification evidence,
and enabling it should not force a full Linux-bundle rebuild.
The OpenC906 user manual states mxstatus.MAEE resets to 0, but the RTL
(aq_cp0_ext_csr.v) resets it to 1. With MAEE set, S-mode page attributes
come from the T-Head extended PTE bits [63:59], which a stock mainline
kernel never programs, so every translated page is non-cacheable; the
C906 then raises a store/AMO access fault (cause 7) for any AMO on such
a page (aq_lsu_ag.v: !mmu_ca && ag_pipe_amo). The first victim was
set_cpu_online()'s amoor.d.aqrl on __cpu_online_mask, after which the
kernel entered the do_trap_break storm before its first console print.
Bare-metal Sv39 payloads proved independently that page-table walks,
loads/stores, and the bus fill path are correct (4 KiB three-level,
2 MiB megapage, high-half canonical VAs, cold fills from SDRAM after D$
eviction); the failure was purely the AMO-on-non-cacheable rule, and no
bus error response or PMP denial was observed on probes.
early_init now clears mxstatus.MAEE so translated accesses follow the
sysmap override (RAM cacheable, MMIO strong-order device) and the stock
kernel needs no T-Head PBMT errata. Evidence: directed payload passes
the full AMO battery (amoor/amoadd/amoswap/lr-sc, cold-line and
high-half-VA variants); hp-linux-sim (bounded 2 h wall) boots past
set_cpu_online, prints 'Linux version 6.12.105+', and keeps retiring
into meminit with no further traps. Userspace acceptance continues on a
longer bounded run; the target stays unqualified until it completes.
The retrosoc_hp platform registered no irqchip_init hook, so the
C906-internal PLIC (thead,c900-plic, decoded by the core BIU rather than
the SoC fabric) was never initialized before the kernel probed it. Select
FDT_IRQCHIP_PLIC and register fdt_irqchip_init: OpenSBI v1.9's
thead,c900-plic match applies the T-Head M-to-S delegation quirk that
S-mode external-interrupt delivery requires. Verified by nm on the
rebuilt fw_jump.elf (fdt_irqchip_init/fdt_irqchip_plic linked in).
- Introduced for formal verification of fault handling in the Tiny R2 P5 architecture.
- Added to test target reset isolation and ensure proper handling of reset signals across multiple targets.
- Created to validate system-level interactions, including CPU and DMA progress during resets.
- Enhanced to include fault counting and master tracking for concurrent fault events.
- Developed to automate testing of concurrency, fault accounting, and retained-image acceptance.
- Updated Python test suite to validate new configurations and ensure proper integration with Tiny R2 P5 architecture.
hp-rtthread-sim now passes on the OpenC906 HP core with all selftest
markers (6,373,952 cycles in 542 s), exercising the internal CLINT
timer/MSWI and the internal PLIC mailbox doorbell. The RT-Thread
bring-up root-cause chain (mcor/mhcr init, sdram_axi4 and crossbar WRAP
handling) is recorded with its regression locks.
hp-linux-sim ran with a bounded 4 h wall budget (158.7 M cycles):
OpenSBI v1.9 completes on the repo-owned retrosoc_hp platform and hands
off to the kernel correctly; the kernel enters S-mode with Sv39 but
stalls in the S-mode fault path after the __cpu_online_mask store page
fault (A/D-bit emulation fixup loop), which is the current bring-up
frontier. The target stays unqualified; the synthesis-dependent gates
remain deferred to the SRAM macro swap round. Also records the latent
gap that OpenSBI never initializes the C906-internal PLIC (no
.irqchip_init), harmless for the current minimal acceptance.
The Mini HP core is the locked OpenC906 with T-Head XTheadCmo custom-0
dcache maintenance; the former rv64imafdc_zicbom_max VexiiRiscv
configuration survives only as the frozen Std-series generator asset.
Sweep the leftover wording:
- scripts/README.md gains the missing setup_openc906.py and
generate_openc906.py entries (locked source install; sha256-pinned
overrides; single compilation unit below build/).
- configs/README.md and app/README.md describe the OpenC906 core and
XTheadCmo maintenance instead of VexiiRiscv RTL generation and Zicbom.
- The npu-p5-hp-sim help line and the npu_p5_report.py emitted HP
evidence mode now say polling-xtheadcmo, matching the payload's
actual dcache.cva/iva mechanism.
The C906 resets with caches and the BPU disabled (mhcr=0) and does not
initialize the cache/predictor RAMs (aq_cp0_ext_csr.v). The upstream
reference crt0 (openc906 smart_run/tests/lib/crt0.s) invalidates them
via mcor before enabling mhcr; skipping mcor makes the core execute
through uninitialized predictor/cache state (wild control flow with no
trap), and leaving caches off makes SDRAM execution ~100x slower, which
livelocked the RT-Thread 1 kHz tick ISR before the first selftest
marker.
Apply the upstream sequence at the earliest point of both HP boot
paths: RT-Thread start.S and the OpenSBI platform early_init. MMIO
windows stay strong-order non-cacheable via the sysmap override, so
enabling the D-cache is safe. hp-rtthread-sim now passes with all
selftest markers (6,373,952 cycles in 542 s).
The OpenC906 is the first master to issue WRAP bursts (cache line fills
start at the critical word). Two latent path bugs made every such fill
fail or corrupt data:
- sdram_axi4 reconstructed the WRAP wrap-back address from the
decrementing remaining-beat count, which cannot reproduce the wrap
boundary; mid-line starts read the second half from wrong addresses.
Beat stepping now uses the registered original geometry through the
proven shared axi4_addr_gen, on both the read and write paths.
- axi4_data_crossbar burst_legal computed a WRAP burst's last address
as if it were INCR, so fills starting in the last 64 bytes of a 4 KiB
page were faulted as FaultProtocol and answered with DECERR. The WRAP
last address is now computed from the wrap boundary.
Locked by new directed cases: mid-line WRAP read/write with
address-encoded data in tests/rtl/sdram_data_tb.sv and a page-edge WRAP
read routing case in tests/rtl/axi4_data_crossbar_tb.sv. Both fail on
the pre-fix RTL and pass after; full test_axi4/test_sdram (17/17),
hp-smoke-sim, hp-rtthread-sim and the PR ci_smoke all pass with the fix.
- Updated SRAM instance paths in to reflect new hierarchy.
- Enhanced to include additional source files and updated parameterized tests for SRAM configurations.
- Modified to align with new SRAM structure and added a test for stale macro hierarchy.
- Introduced to validate dual-port local-memory protocol and CPU debug/reset functionality, including comprehensive simulation checks.
- Adjusted slot assignments in to reflect new peripheral mappings.
- Updated to validate new OpenC906 configurations, including generator and profile checks.
- Modified to reference the new Std-series VexiiRiscv generator.
- Changed cache maintenance instructions in to align with C906 specifications.
- Revised assertions in to account for internal unit removals.
- Updated to reflect changes in peripheral interface counts and policies.
- Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
- Implemented tests for WS2812 DMA sessions and refill functionality in .
- Added a new RTL testbench for WS2812 refill functionality in .
- Enhanced AXI4 data crossbar testbench to diagnose MMIO boundaries for the Mini DMA.
- Created a new Python test suite for Tiny R2 P3 to validate firmware warnings and layout placements.
- Updated existing WS2812 tests to parameterize and check for DMA backpressure integration.
- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Updated tiny-soc.md to reflect the 2026-10-07 refreeze, establishing ICS55 as the default target PDK with HAVE_PLL=YES.
- Added detailed sections on final timing gate policies, PLL integration, and execution order for Tiny SoC.
- Modified soc-family-positioning.md to indicate the new default target for Tiny as ICS55/PLL while maintaining IHP130 compatibility.
- Enhanced pdk/README.md and setup.py to support the integration of the locked ICS55 PLL views, including setup commands and validation.
- Introduced tests for the ICS55 PLL dependency to ensure proper integration and validation of PLL views.
- Updated rtl/tiny/README.md to clarify the current executable baseline and the pending integration of ICS55.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling.
- Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels.
- Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses.
- Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic.
- Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.
- Updated the tiny-soc-verification.md to clarify the separation of PIO-lite as a standard-product extension, detailing its planned features and evidence requirements.
- Revised tiny-soc.md to emphasize the historical context of the R2 design freeze and the independent nature of the PIO-lite extension, including its integration requirements and phase structure.
- Added details in soc-family-positioning.md regarding the PIO-lite extension's capabilities and its distinction from the R2 performance-only approval.
- Enhanced README.md files in rtl/ip and rtl/tiny to reflect the future integration of the PIO-lite extension, specifying its features and the implications for existing RTL and DMA configurations.
- Clarified integration details for WS2812 and XPI in respective documentation.
- Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels.
- Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts.
- Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
- Added details on the Tiny Gen1 target's shared XPI register/LUT/PHY contract and optional NSS1 PSRAM integration.
- Clarified the memory model to include optional initialized XPI NSS1 PSRAM for whole-frame data.
- Updated the edge I/O section to reflect the alternate DVP V2 camera profile and GPIO allocations.
- Revised the shared services and package specifications to align with the latest P10 refreeze.
- Enhanced the README to include P10 documentation refreeze details, emphasizing DVP V2 contract and PSRAM integration.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets.
- Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations.
- Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details.
- Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
- Introduced a new maintenance reference for dependency and environment routing.
- Enhanced the feature implementation skill with migration references for behavior-preserving changes.
- Added regression and RTL migration references to support feature review processes.
- Created a new physical flow skill with detailed execution and recovery guidelines.
- Updated evals for feature implementation and review skills to include new scenarios.
- Improved the AGENTS.md and tests to reflect the new skills and references.
- Added new skills for retroSoC feature implementation and review, including YAML configurations and evaluation cases.
- Removed deprecated mini feature design and implementation skills.
- Updated documentation to reflect changes in skill names and functionalities.
- Adjusted test cases to ensure compatibility with the new skill structure and validate the presence of required files and metadata.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities.
- Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi.
- Enhanced register reference parsing to accommodate Tiny-specific memory maps.
- Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs.
- Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims.
- Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Clarified P5 capabilities including direct/ring WAV/FLAC jobs and new KWS model integration.
- Specified requirements for evidence acceptance related to P5 enhancements.
- Noted that P6 MP3 support remains deferred with emphasis on design requirements.
- Updated details on P9 refreeze requirements, including macro-backed storage and future obligations.
- Reinforced that existing system clock/reset/IRQ/resource assignments remain unchanged.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced to define the development environment and validate runtime/platform contracts.
- Enhanced with to ensure change markers adhere to publication rules.
- Updated to integrate boot acceptance checks and ensure dependencies are correctly managed.
- Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards.
- Implemented checks in to validate the presence of development environment dependencies.
- Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
maksyuki