Add standalone RAW/PROCESS routing, DVP source qualification, and lifecycle guards for Tiny captures. Harden APB/CDC close races and preserve Mini/default RAW compatibility with explicit unused-output tie-offs.
Validation: 2488 host tests, 161 focused tests, 18 RTL/netlist scenarios on both PDKs, formal BMC/cover, dual-PDK reports, Mini behavioral PR, and Tiny IHP130 full PR regression. Timing remains observational; no closure claim.
Record the reviewed 6f5638ff checkpoint and all seven successful CI runs. Summarize the final dual-PDK evidence, exhaustive/PL-V/formal coverage and three clean review rounds while keeping generated phase_accepted records false and P3+ qualification gaps explicit.
Implement the standalone two-SM PIO-lite core, shared 32x16 IMEM, per-SM 8x32 FIFOs, APB1.0/ISA1.0 register mirror, GPIO guard and local stream lifecycle adapters. Keep Tiny integration, central DMA, HAL loader, profiles, dependencies and warning baselines unchanged.
Add exhaustive 65536-word differential testing, directed/random PL-V coverage, exact SVH/C parity, formal proofs and named witnesses, plus fail-closed dual-simulator, synthesis, netlist and observational STA flows. Three independent review rounds closed all findings, including lifecycle coverage and evidence-integrity gaps. Final IHP130 and ICS55 stage reports pass; phase_accepted remains false.
Record PIOLITE-P1 acceptance at dev@921a4abf with all seven CI workflows successful on the follow-up CI repair 449829e1. The standing development goal authorizes automatic acceptance recording when independent review is clean and CI is green. Summarize the model/assembler evidence, exhaustive ISA checking, application footprints, and the seven review rounds' closures; generated records keep phase_accepted=false while acceptance is recorded here.
The OpenC906 datasheet refresh added publication tests and collectors that read the locked OpenC906 source tree, but quality CI never installed it, leaving 89 failed/error entries on dev@65028468 and dev@921a4abf while local runs passed with a populated cache. Add scripts/setup_openc906.py to the locked RTL dependency step and cache .cache/retrosoc/sources/openc906 so restored runs also see it. No dependency lock, test, or source change.
Validation: a clean detached worktree at 921a4abf reproduced the failures (5 failed, 17 errors); after provisioning the locked OpenC906 checkout plus the existing managed dependencies, tests/test_publication_c906_refresh.py and tests/test_publication_implementation.py pass 55/55. yamllint, actionlint and both regression dry-runs pass.
Add the frozen ISA1.0 host tooling for TINY: checked 16-bit encode/decode with relocation and atomic 32-slot allocation/sharing (scripts/piolite_isa.py), a two-SM PCLK reference model with DIV/delay, wrap/HALT, lifecycle, shift/autopull/autopush, pre-edge FIFOs and latched faults (scripts/piolite_model.py), and a strict .piolite assembler with deterministic C objects and atomic output (scripts/piolite_asm.py). Ten handwritten application programs under app/asm/piolite/ prove real 32-word footprints: pulse generate+capture 20/32, UART TX+RX 24/32, IR TX+RX 23/32. No RTL, HAL, profile, dependency or public-ABI changes; no protocol/rate qualification is claimed.
Validation: 176 focused tests including exhaustive 65536-word ISA checking (22257 legal/43279 rejected), full 16-delay matrix, lifecycle/publication/authorization coverage and independent application behavior tests; full Pytest 2300 passed, 1 skipped; ruff, C11 syntax checks and byte-identical rebuilds pass. Seven independent review rounds closed twelve defects and three coverage gaps, all re-verified by independent probes; findings and closure evidence are recorded in docs/ip/piolite-verification.md with phase_accepted=false.
Reconcile the Mini v0.5 DRAFT with the reviewed OpenC906 source snapshot,
including the single AXI128 path, internal CLINT/PLIC, interrupt IDs,
startup/cache behavior, and SRAM/clock-gating boundaries. Preserve all
42 IP chapters, 109 structure entries, and the prior register corrections.
Add source-bound extraction guards and negative tests, and update the
publication guide, layout rules, content assessment, and chapter review.
Keep historical validation and missing hardware evidence explicitly scoped.
Validation: current Ruff, staged diff checks, and 397 local documentation
links passed. The recorded 796-page publication passed 611 publication
tests, 37 C example checks, color/grayscale inspection, and byte-identical
offline reproduction. The earlier full suite retained 2104 passes,
42 failures, 65 setup errors, and 7 skips; subsequent publication checks
resolved its publication cases without claiming a full-suite or hardware pass.
The maintainer confirmed human acceptance of SPI-P4 sub-stages A and B at dev@31e38614 with all seven CI workflows successful. Record the accepted checkpoint, the four-leg A+B simulation matrix, the live-admission repair, V22 measurements, the closed independent-review findings, and the unchanged coverage gaps (Icarus full-A geometry, legacy LCD/LVGL gate, check-rtl-lint baseline, synthesis/netlist/STA/physical deferred to SPI-P5). Generated records keep phase_accepted=false; acceptance is recorded in this ledger.
Record the sub-stage B command/verdict matrix for both profiles and both simulators, the SRAM/PSRAM V22 measurements, the live-admission root cause and repair, the partial-abort oracle and progress-reassembly corrections, the independent review findings (exact abort-length enforcement, new negative fixtures) and their closure, and the remaining gaps (Icarus full-A geometry, legacy LCD/LVGL gate absence, check-rtl-lint baseline absence, synthesis/netlist/STA/physical deferred to SPI-P5). phase_accepted stays false; the rejected 14:51 run remains labeled as rejected.
Implement SPI-V21/V22 on the committed SPI-P3/P4A base: immutable-buffer ST7789VI display with DMA-bound feeds from PSRAM or bounded SRAM chunks, QVGA capture into capacity-checked XPI NSS1 PSRAM, sequential capture/verify/display/native-SD save with readback, DMA-aware wire-abort versus bound-DMA abort/drain recovery, and SRAM-versus-PSRAM measurements (SCK, frame/CPU cycles, utilization, FIFO levels, longest stalls). Bounded static workspaces only; no heap, no full frame in SRAM, no new register ABI or dependency.
Verification: the P4 image passes full A+B on both profiles with Verilator (94425948 cycles) and Icarus QUICK-A (53810943 cycles), zero forbidden markers and independent checker problems=[]. The panel oracle now distinguishes legal partial-frame aborts from invalid truncation while still rejecting complete-window odd bytes and residual bits; the checker enforces exact 544/143-pixel abort lengths and reassembles progress-interleaved records losslessly. Host C tests, 22 focused tests, and the full 2124-test Pytest suite pass; P3 acceptance remains passing on both profiles.
The integrated DMA statically enabled SPI request readiness, so a fast SRAM source could issue fixed-MMIO writes while the SPI TX FIFO was full (fault 4 at 0x1001d054), violating the frozen admission-reservation contract in docs/ip/dma.md and docs/ip/spi.md. apb4_spi now exports live TX/RX admission qualified by the enabled binding, FIFO readiness and absence of pending credit/response; dma_core gates only SPI requests 16/17 with it; spi_start_pending_o follows registered busy jobs to avoid a combinational readiness loop. Mini and SPI-disabled wrappers tie the new input off; scheduler, burst behavior, credit reservation/retirement and register ABI are unchanged.
Evidence: new SPI-V12 dynamic admission test passes on Verilator and Icarus (tx_full/rx_empty/delayed_R/delayed_B/abort_inflight); Mini lint and DMA formal prove/cover pass; DMA/WS2812/P9 consumer tests 11 passed; the full SPI-P4B A+B workload passes on both profiles and both simulators with zero forbidden markers.
The maintainer confirmed human acceptance of TINY-R2-P8, TINY-R2-P9 and TINY-R2-P10 at dev@4466ad0e with all seven CI workflows successful. Record the refreshed evidence roots, the zero-gap single-timestamp ICS55 P10 report, the shared execution source digest, and the unchanged deferrals (long Icarus firmware, full PR/nightly regression, physical/PVT/board qualification, final timing closure). Generated collector records keep phase_accepted=false; acceptance is recorded in this ledger.
The compact DVP gate-model simulation now needs 12.9-13.3k seconds on the current netlist, exceeding the previous 10800s default and ending in host timeout (exit 124) without a DUT error marker, including on an otherwise idle host. Raise the ICS55 TINY_P9_NETLIST_WALL_TIMEOUT default to 14400s; IHP130 stays at 7200s and the 300000-cycle guard, image, and payload checks are unchanged.
Verified with fresh full backend chains in the R2-P9 and R2-P10 collectors: netsim-dvp passes with SIM_TEST_PASS Tiny cycles=177541 in 12886.6s (P9) and 13317.1s (P10), each with exactly one pass marker and zero forbidden markers.
The merged HP subsystem makes the Mini ci_smoke ld2_sdram Verilator step
need roughly 4400 s locally (SIM_TEST_PASS code=0 in 4389 s,
build/ics55-2026-10-23-15-17-2e059475a01b/), so hosted runners time out the
existing 3600 s tier during the crypto self-test on ICS55/SKY130/GF180
(jobs 120251738572, 120251738799, 120251738649). Double the tier to 7200 s;
the ld2_all_sram step stays at 3600 s (measured need about half of that).
Validation-only budget change with the two contract assertions pinned to the
new values; no RTL, firmware, or marker-rule change.
The feat/mini-hp-core merge adds the HP subsystem to the Mini Verilator
model, so the ci_smoke acceptance step (which ends in the crypto self-test)
exceeds the old 1800 s wall budget on hosted runners and fails with
SIM_TEST_TIMEOUT. The merged content is functionally correct: the identical
step passes locally with SIM_TEST_PASS code=0 in 1806 s wall
(build/ihp130-2026-10-23-11-20-cff97749f2f3/). This is a validation-only
budget change to the existing 3600 s tier already used by the SDRAM variant;
the contract tests in tests/test_script_tools.py are updated to pin the new
value. No RTL, firmware, or marker-rule change. CI failure under repair:
regression-ihp130 run 39889921334.
Regenerated from a successful merged-source Verilator lint run
(build/ihp130-2026-10-23-08-35-f2c2308f4da3/lint/verilator/lint.log) after
the feat/mini-hp-core merge. Reviewed normalized signatures: new entries are
attributable to the merged HP core content (openc906 combined source), Mini
wiring of newer shared-IP pins (apb4_gpio taps, apb4_system clock hz), and
the dma_reg SupportedRequests parameter from the shared DMA V2.2 work; eight
stale signatures resolved. Kept separate from the contract fix per the
baseline policy. check-rtl-lint passes after regeneration
(build/ihp130-2026-10-23-08-36-f2c2308f4da3/meta/rtl-lint-warnings.json).
The feat/mini-hp-core merge brought in the HP_JTAG_DEBUG knob's boot block,
which predates two checked publication contracts that neither side had
updated: the boot preprocessor review only allowed the NPU conditions, and
the boot diagnostic list/namespace ended at code 19. Align them with the
merged content: accept defined(RS_HP_JTAG_DEBUG) in
publications/boot_acceptance_reference.py, add fail code 20 to
expected_direct and its meaning in publications/datasheets/system-reference.json,
extend the boot namespace to range(21) in tests/test_publication_retrieval.py,
and write the knob's guard in main.c in the reviewed '#if defined(...)' form
(identical preprocessor semantics).
Validation: the publication suites pass (122 passed, 1 known pypdf skip);
format/policy/host gates clean.
Add the frozen display path on top of the committed SPI-P3 integration:
the project-owned ST7789VI four-wire adapter in app/board (held-CS
command/data chains, D/C at clean boundaries with readback, bounded
workspaces), the TINY_SPI_P4_ACCEPTANCE ci_smoke image (discovery, panel
init ordering, color bars, gradient, odd rectangles, rotation variant,
abort/recover/release/reacquire case, measurements), the pin-independent
panel oracle rtl/tiny/dv/tiny_st7789_panel.sv, the golden geometry/pixel
checker scripts/spi_p4.py, pytest contracts tests/test_spi_p4.py and the
st7789vi host tests. The runbook is docs/ip/spi-p4.md.
Validation: Verilator acceptance passes on both Tiny profiles at
SIM_TEST_PASS Tiny cycles=43019427 (build/ics55-tiny-2026-10-23-01-37-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-38-616e0604657d/) and Icarus behavioral
passes on both profiles with the documented QUICK delay/geometry variant at
cycles=2710932 (build/ics55-tiny-2026-10-23-01-34-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-39-616e0604657d/); the independent golden
checker reports zero problems on all four logs (8/8 windows, pixel counts
and FNV-1a checksums, violations=0); full Pytest 2102 passed, 0 failed,
1 skipped; C format/policy/host and RTL format gates clean.
Sub-stage B (PSRAM-source display, sequential capture/verify/SD save,
SRAM-vs-PSRAM performance) remains gated on R2-P8/R2-P9 human acceptance.
SPI-P5 remains deferred; phase_accepted stays false. Recorded in
docs/ip/spi-verification.md.
Three defects found by SPI-P4 display bring-up in the committed SPI-P3
integration and HAL, each root-caused with log-level evidence:
- retrosoc_tiny.sv wired the SPI gpio_ready_i to the GPIO APB bridge's
transaction-level ready, which drops for the whole CDC round trip of every
GPIO register access. The frozen D/C contract requires GPIO30 writes
between segments during a session, so the guard latched fault 2 and closed
the session on the first D/C change. The readiness scope per the frozen
text is GPIO clock/reset availability; the expression is now
s_gpio_rst_n && !s_actual_gate[1], stable during a session.
- rs_spi_acquire returned after GPIO_READY alone, before the enable gap
reached IDLE; the first ARM could then be rejected. It now also waits
BUS_IDLE, so an acquired session is immediately usable.
- rs_spi_recover waited for ownership to clear, but RECOVER retains the
session per the ABI; it now waits for wire-state Disabled. rs_spi_release
unconditionally issued DISABLE, legal only from IDLE; from the
post-recover Disabled state it now goes straight to pin restore and
RELEASE.
Validation: SPI-P3 acceptance re-run passes after the HAL changes
(SIM_TEST_PASS Tiny cycles=1037899); the SPI-P4 display acceptance passes on
both profiles and both simulators with these fixes in place
(build/ics55-tiny-2026-10-23-01-37-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-38-616e0604657d/ and the Icarus QUICK
variants); full Pytest 2102 passed, 0 failed; C format/policy/host gates
clean. No ABI or Mini change.
The Verilator testbench tied the HP console UART1 RX pin directly to its
TX pin, so every byte the C906 transmitted looped back into the UART1 RX
FIFO. The Linux kernel's hvc console (hvc0) is a TTY with ECHO enabled;
its __hvc_poll thread reads the looped-back bytes and the N_TTY line
discipline re-emits them. The result is a feedback loop that re-prints
the console output repeatedly with progressive character loss (the
OpenSBI banner appearing four times, degrading into truncated fragments
and thousands of blank lines in the boot log).
Hold the RX pin idle (no external input) so console_getc always reports
no input and the echo loop never starts. uart0 (the LP console) is
unconnected on both pins and was already unaffected.
Evidence: hp-linux-sim on configs/ci/ihp130-hp.mk (Verilator) now shows
the OpenSBI banner exactly once with no blank-line artifacts, and still
completes userspace acceptance (HP_LINUX_INIT_PASS, retroSoC HP Linux
ready, HP_LINUX_READY, SIM_TEST_PASS code=0; 1.56 G emulator cycles,
status: passed with no missing markers).
The Tiny Icarus flow compiles only the sv2v-lowered converted_soc.v, where
packed structs become plain vectors and interface ports dissolve, while the
dv observers read struct fields hierarchically and tiny_p9_recovery.svh used
a string case that crashes Icarus code generation. Elaboration failed with
29 errors on both profiles (CI runs 39719773195 and 39719773217).
Keep every observer semantically identical: move a time declaration above
its first use in tiny_p8_observers.svh, read the identical packed bit ranges
through named slice constants in tiny_p9_observers.svh and
retrosoc_tiny_tb.sv (valid in both the Verilator struct view and the sv2v
vector view), read the XPI APB wires through the top-level interface
instance u_xpi_apb4_if (the same nets), and rewrite the string case as an
exact-match if/else chain. No DUT, Mini, baseline, or verdict-rule change.
Validation: Icarus compile clean on both profiles; the R2-P7 Icarus
behavioral acceptance passes with SIM_TEST_PASS Tiny cycles=3859487
(build/ihp130-tiny-2026-10-22-12-16-aae2707c2aa5/sim/iverilog/), matching
the Verilator cycle count exactly; SPI-P3 acceptance (cycles=1030088 on both
profiles) and R2-P7 Verilator acceptance (cycles=3859487) are unchanged;
full Pytest 2097 passed, 0 failed, 1 skipped; formatting gates pass.
Evidence recorded in docs/ip/tiny-soc-verification.md.
The SPI-P3 guard and source additions introduced longer variable names
(TINY_SPI_P3_ACCEPTANCE), so mbake realigns the affected assignment blocks
in Makefile, app/apps/ci_smoke/tiny.mk and rtl/mk/software.mk. Formatting
only; no functional change. Fails the quality gate's mk-format-check
otherwise (CI run 39719773198).
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at
0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes,
latched four-bit source qualification through the fabric and APB CDC, GPIO
readiness/ownership guard, and the bounded rs_spi_* HAL with the
TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17
with exact fixed FIFO MMIO checks; Mini remains default-disabled and
unchanged. Review closure: the DMA AXI4 master stages the origin channel with
each burst so final and contended SPI alias bursts stay qualified, the RCU
spare feedback bit is tied off for four-state simulators, and the
clock-switch quiescence now includes the SPI session.
Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf);
both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS
cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and
cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass;
C format/policy/host tests and RTL format/style checks clean. Evidence and
remaining obligations are recorded in docs/ip/spi-verification.md.
Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v
defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is
skipped per maintainer decision. Human phase acceptance and SPI-P4/P5
remain outstanding; phase_accepted stays false.
The vendored BIU streams a writeback's W data as soon as the victim
buffer offers it (AXI-legal W-before-AW), while the AW still waits in
awbuf for the serializing 128->64 downsizer to finish the previous
write (the ~200-cycle SDRAM write response latency). The Mini HP
fabric behind the pad is single-outstanding (downsizer + MMIO demux +
target guard, no WID), so the early W beats are absorbed into the
previous write's burst; each write's AW then arrives to find its W
already consumed by the previous write's stream. The cascade persists
until the LSU freezes (its fills block behind the SDRAM write channel,
which is parked waiting for the orphaned write's W data), leaving a
final orphaned AW whose W beats never come: the target guard parks in
WriteStream, the SDRAM core parks in its write-data state and blocks
the pending read fill, and the C906 stalls at the next LSU-serializing
instruction.
Event-level tracing pinned the mechanism: with the guard parked, the
C906 write side is fully idle (victim buffer idle, store buffer idle,
BIU write-selection FIFO empty, zero W beats presented at the 128-bit
port for the wedged write) while the guard and the SDRAM controller
both hold the orphaned write's AW.
The rtl/mini/ip_overrides/aq_biu_write_channel.v override gates the W
stream on the burst's AW having been issued on the pad (pad-issued-AW
vs completed-W-burst order counters), restoring the AW-before-W order
the fabric requires without touching the vendored checkout. The
generator registers the override under the pinned sha256 guard, and
the Makefile stamps it as a dependency.
Evidence: the deterministic wedge payload and the no-fence control run
unbounded (previously wedged at ~22 rounds); hp-smoke-sim and
hp-rtthread-sim pass (SIM_TEST_PASS code=0); hp-linux-sim completes
userspace acceptance (Run /init as init process, HP_LINUX_INIT_PASS,
retroSoC HP Linux ready, HP_LINUX_READY, SIM_TEST_PASS code=0, 1.63 G
emulator cycles, status: passed with no missing markers); pytest
tests/test_hp_platform.py passes 20/20. docs/hp-rv64-validation.md
records the mechanism and the acceptance.
Document the standalone interfaces, timing checker, FIFO pressure cases,
tool-component identity and exact execution commands. Update subsystem
guides and the verification ledger with the matching ICS55/IHP130 evidence.
Keep historical failures and producer identities separate from the new
results. Record the optional PDF-test skip, unconstrained IO boundaries,
deferred full-product regressions and the human phase-acceptance gate.
Validation: 21 local links and the documentation-only post-test delta
checked; git diff --check passed. No generated evidence is committed.
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB
responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session
abort/recovery. Add the handwritten SVH/C register mirror and private
source, credit and GPIO qualification interfaces.
Add independent pin timing and data checks, malformed-waveform negatives,
FIFO stall/resume and phase-safe abort cases. Provide isolated lint,
simulation, compositional formal, synthesis, netlist and observational STA
flows with source-bound artifacts and tool-component fingerprints.
Validation on the reviewed worktree: 2085 pytest tests passed and one
optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and
cover, and ICS55/IHP130 block synthesis and netlist simulation passed.
Formatting, style/readiness, Ruff and regression dry-runs passed.
SPI remains outside product filelists with DMA capability disabled.
SPI-P2/P3 integration, full-product regression closure and physical/IO
qualification remain pending; no phase acceptance or policy change.
Document the P10 workload, profile selection, exact command matrix,
single-execution policy and retained source/binary identities. Record
matched performance, camera/audio/backend results, P7 and VGA follow-ups,
and the approved quality repairs with their original phase attribution.
Preserve failed attempts and distinguish later successful checks from
historical evidence. Record 2031 passed / 1 skipped for the final Pytest
run, five firmware builds and four byte-identical Tiny HEX comparisons.
Keep phase_accepted=false. Full long Icarus and complete supported
regression, publication/PDF readiness and final physical/PVT/board/sensor
qualification remain open; observed timing is not timing closure.
Validation: documentation links and commands checked; git diff --check
passes. The existing evidence remains bound to its pre-commit revision.
Follow the shared PSRAM model path and bind the DVP DMA selector together
with its Tiny/Mini definition, preserving Mini bulk-channel semantics.
Describe the 129-bit configuration/epoch CDC packet, 128-bit payload
extraction and applied register using the existing RTL. Complete isolated
fixture dependencies and add negative checks for channel, width, slice
and register-bypass drift without relaxing source validation.
The final publication selection passes 163 tests with one optional skip;
the full final worktree passes 2031 tests with the same pypdf skip.
Retain publication identity and strict source-drift checks. No RTL, PDF
generation, source-baseline refresh or physical qualification is included.
Require the implemented DVP-inclusive 0x7fff target set in the P7
acceptance image. Preserve the exact startup comparison and keep the
architectural allowed mask separate from implemented capabilities.
Add cross-source checks against the real SYSCTRL instance and negative
cases for stale, expanded, missing, ambiguous or weakened expectations.
Production capability bits and the HAL ABI are unchanged.
The focused 14-test selection and both ICS55/IHP130 P7 Verilator runs
pass strict Tiny terminal, lifecycle and profile checks. The final
worktree also passes 2031 Pytest tests with one optional pypdf skip.
Add an isolated SAFE24 QVGA capture, CPU statistics and SDIO save/readback
image with passive transaction observers. Keep ordinary images, production
RTL, public interfaces and dependency versions unchanged.
Retain matched binaries and source-bound stage evidence, distinguish
software comparisons from architectural measurements, and reject invalid
terminal results or incompatible resume inputs. Count SDIO descriptors and
status writebacks separately from pixel payload.
Validation on the final worktree includes 2031 passed / 1 skipped Pytest
tests, C format/policy/host checks, and directed observer tests on Icarus
and Verilator. Selected ICS55 and IHP130 SAFE24 campaigns and compact
backend checks pass; negative STA and warning observations are retained.
Complete P10 acceptance remains pending final regression and human review.
Specification: docs/ip/tiny-soc.md, TINY-R2-P10.
Remove one final LF from four Make files to satisfy the existing mbake
1.4.6 configuration. Preserve all other bytes and keep the independent
P10 implementation out of this formatting commit.
Final-worktree validation confirms identical configuration and command
expansion for five firmware variants, including the Mini lint dry-run.
Format, software policy and host checks pass. The existing editorconfig
newline discrepancy remains a separate policy issue.
Document the DVP integration contract, reviewed remediation and source-bound
ICS55/IHP130 evidence, preserving original phase IDs and historical runs.
Record matched firmware binaries, current functional results, observational
STA, warning deltas and unresolved global quality/qualification gaps.
Evidence was produced from 39ae718 plus the archived worktree; retain that
provenance rather than relabeling earlier runs with new commit identities.
P9 human acceptance remains pending. This documentation does not advance P10
or qualify a physical operating point.
Validation: read-only artifact/source hash review and git diff --check.
Add isolated default and camera LibreLane IO profiles, assigning camera
inputs to the pixel clock and keeping ordinary GPIO constraints in default.
Separate generated output roots and synchronize the commercial clock-domain
inventory with the P9 DVP domain.
Retained validation: nine LibreLane scenario tests and 50 commercial-flow/
Tiny reset-inventory tests pass. Constraints retain development assumptions;
no commercial EDA, physical signoff or board timing qualification is claimed.
Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
Connect DVP to Tiny DMA2/request 11, IRQ15 and the camera pad/reset lifecycle.
Harden shared capture CDC, frame statistics, per-row size validation and HAL
cleanup while preserving the Mini DMA3 binding and existing register ABI.
Add deterministic capture/recovery firmware, source-bound evidence tooling,
focused RTL/host tests and compact netlist acceptance. Preserve SAFE24,
128 KiB main SRAM, private Crypto storage and the locked dependencies.
Retained validation: focused RTL, host/policy checks, Mini firmware, and
ICS55/IHP130 RECOVERY, QVGA, synthesis and boot/DVP netlist checks pass.
Full-system VGA remains historical; long full Icarus and broad regressions
remain deferred. Global publication/format gaps and negative observational
STA are retained, not reported as passing qualification.
Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
Evidence: docs/ip/tiny-soc-verification.md.
Present the complete error bundle on the event sampling edge and clear stale
address and PC fields for rejected requests and polling timeouts. Preserve
register encodings, response latency and first-error snapshot semantics.
Add 12 error/IRQ scenarios for Tiny Icarus, Tiny Verilator and the Mini
Verilator consumer. Retained P9 validation covers these paths; see
docs/ip/tiny-soc-verification.md and docs/ip/xpi.md.
Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md
adds the tiling table (8-bit macro stacking with registered read muxes),
notes the repo-owned functional models versus the vendor collateral in the
locked PDK, and documents the SKY130 byte-mask blocker as the reason that
PDK stays behavioral; hp-rv64-validation.md records the directed-TB,
MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs
generalize the override wording to IHP130/ICS55/GF180. Physical
qualification (Liberty registration, STA, LEC) stays explicitly deferred.
The gf180 boot testbench mode defines PDK_GF180 and therefore now compiles
the SRAM macro branches alongside the ICG cells: add the repo-owned
gf180_sram_sim_cells.sv to its model list and rename the test to
test_c906_boots_smoke_payload_with_gf180_macros. Both GF180 models are
repo-owned, so the mode no longer depends on the PDK checkout.
Evidence: tests/test_hp_platform.py passes 20/20 with all five boot modes
(behavioral, ihp130, ics55, sky130-icg, gf180); the CI-flavored gf180
profile simulation passes at 26,462,456 cycles with SIM_TEST_PASS code=0.
Add a PDK_GF180+HAVE_SRAM_MACRO (without PDK_BEHAV) branch to each of the
eight aq_spsram_* overrides, tiling the 8-bit GF180 macros
(sram{64,128,256,512}x8m8wm1, per-bit active-low WEN, matching polarity so
no inversion is needed): 512x8 tiles with registered read-mux depth
stacking for 1024x16/2048x32/1024x64, width stacks of depth-exact 256x8
and 64x8 tiles for 256x59/64x58/64x88/64x98 (partial top tiles tie unused
WEN bits inactive), and a single exact 128x8 tile for the dirty array.
VDD/VSS follow the tc_sram.sv GF180 convention.
The GF180 CI profile (HAVE_HP=YES, HAVE_SRAM_MACRO=YES, PDK_BEHAV unset)
now compiles the macro path automatically. Behavioral, IHP130, and ICS55
paths are bit-identical. SKY130 intentionally stays behavioral: the locked
OpenRAM macro offers only byte-granular wmask0 while six of the eight C906
arrays require per-bit writes (BHT one-hot, 29/44/48-bit field groups,
single-bit dirty updates).
Evidence: directed 8-wrapper equivalence TB and the MEM_INTF adaptation
pass on the GF180 path; the gf180 boot testbench and the GF180 SoC
hp-smoke-sim both pass (SIM_TEST_PASS code=0, 3,644,186 cycles, identical
to every other macro mode).
Extend gf180_sram_sim_cells.sv with pin-compatible functional models for
gf180mcu_fd_ip_sram__sram{64,128,256}x8m8wm1, matching the existing 512x8
model's style and behavior (registered read, per-bit active-low WEN,
VDD/VSS sanity checks). All four geometries ship vendor collateral in the
locked gf180mcu-pdk checkout; the repo-owned models keep simulation
self-contained per the existing convention. No filelist change: the file
is already listed in pdk_gf180.fl.
Close out the chapter 3 documentation: hp-platform.md gains the ICG
section (three override points, per-PDK cell table, the ICS55 SE-into-E
note, and the two-state reset rationale), leaving only physical/STA
qualification deferred; hp-rv64-validation.md records the MEM_INTF ICG
results, the five boot testbench modes, and the four SoC-level runs with
the remaining gaps; the two READMEs extend the override inventory to
hart-ID + sysmap + SRAM wrappers + clock-gating cells.
The ihp130/ics55 macro-mode boot testbenches define PDK_IHP130/PDK_ICS55,
so they now also compile the ICG branches: extend their model sets with
sg13g2_udp.v+sg13g2_stdcell.v and ics55_h7cr_functional.v respectively
(the latter with +define+functional, mirroring pdk_ics55.fl). Add
test_c906_boots_smoke_payload_with_sky130_icg and ..._gf180_icg covering
the two PDKs whose SRAM wrappers intentionally stay behavioral (mixed-mode
coverage); both skip when the PDK checkout is not materialized.
Evidence: all five boot testbench modes pass with HP_C906_BOOT_TEST_PASS
(5 passed, 634s); whole-SoC macro+ICG runs pass for IHP130 and ICS55
(hp-smoke-sim, SIM_TEST_PASS code=0 with the GA2D lifecycle markers), and
the CI-flavored sky130/gf180 profile simulations pass at 26.46M cycles.
dependabot[bot]