The merged HP subsystem makes the Mini ci_smoke ld2_sdram Verilator step
need roughly 4400 s locally (SIM_TEST_PASS code=0 in 4389 s,
build/ics55-2026-10-23-15-17-2e059475a01b/), so hosted runners time out the
existing 3600 s tier during the crypto self-test on ICS55/SKY130/GF180
(jobs 120251738572, 120251738799, 120251738649). Double the tier to 7200 s;
the ld2_all_sram step stays at 3600 s (measured need about half of that).
Validation-only budget change with the two contract assertions pinned to the
new values; no RTL, firmware, or marker-rule change.
The feat/mini-hp-core merge adds the HP subsystem to the Mini Verilator
model, so the ci_smoke acceptance step (which ends in the crypto self-test)
exceeds the old 1800 s wall budget on hosted runners and fails with
SIM_TEST_TIMEOUT. The merged content is functionally correct: the identical
step passes locally with SIM_TEST_PASS code=0 in 1806 s wall
(build/ihp130-2026-10-23-11-20-cff97749f2f3/). This is a validation-only
budget change to the existing 3600 s tier already used by the SDRAM variant;
the contract tests in tests/test_script_tools.py are updated to pin the new
value. No RTL, firmware, or marker-rule change. CI failure under repair:
regression-ihp130 run 39889921334.
Add the frozen display path on top of the committed SPI-P3 integration:
the project-owned ST7789VI four-wire adapter in app/board (held-CS
command/data chains, D/C at clean boundaries with readback, bounded
workspaces), the TINY_SPI_P4_ACCEPTANCE ci_smoke image (discovery, panel
init ordering, color bars, gradient, odd rectangles, rotation variant,
abort/recover/release/reacquire case, measurements), the pin-independent
panel oracle rtl/tiny/dv/tiny_st7789_panel.sv, the golden geometry/pixel
checker scripts/spi_p4.py, pytest contracts tests/test_spi_p4.py and the
st7789vi host tests. The runbook is docs/ip/spi-p4.md.
Validation: Verilator acceptance passes on both Tiny profiles at
SIM_TEST_PASS Tiny cycles=43019427 (build/ics55-tiny-2026-10-23-01-37-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-38-616e0604657d/) and Icarus behavioral
passes on both profiles with the documented QUICK delay/geometry variant at
cycles=2710932 (build/ics55-tiny-2026-10-23-01-34-106e35060a8e/,
build/ihp130-tiny-2026-10-23-01-39-616e0604657d/); the independent golden
checker reports zero problems on all four logs (8/8 windows, pixel counts
and FNV-1a checksums, violations=0); full Pytest 2102 passed, 0 failed,
1 skipped; C format/policy/host and RTL format gates clean.
Sub-stage B (PSRAM-source display, sequential capture/verify/SD save,
SRAM-vs-PSRAM performance) remains gated on R2-P8/R2-P9 human acceptance.
SPI-P5 remains deferred; phase_accepted stays false. Recorded in
docs/ip/spi-verification.md.
Integrate the SPI-P2 shared-DMA ABI into the Tiny product: SPI0 at
0x1001D000 with IRQ25 and RCU target16, the four frozen Gen1 ALT routes,
latched four-bit source qualification through the fabric and APB CDC, GPIO
readiness/ownership guard, and the bounded rs_spi_* HAL with the
TINY_SPI_P3_ACCEPTANCE ci_smoke image. Tiny DMA enables V2.2 requests 16/17
with exact fixed FIFO MMIO checks; Mini remains default-disabled and
unchanged. Review closure: the DMA AXI4 master stages the origin channel with
each burst so final and contended SPI alias bursts stay qualified, the RCU
spare feedback bit is tied off for four-state simulators, and the
clock-switch quiescence now includes the SPI session.
Validation: full Pytest 2097 passed, 0 failed, 1 skipped (optional pypdf);
both Tiny profiles pass the SPI-P3 Verilator acceptance (SIM_TEST_PASS
cycles=1030088); R2-P7 Verilator acceptance, Mini DMA formal prove and
cover, Mini/Tiny lint, Tiny Yosys synthesis, netsim-boot and OpenSTA pass;
C format/policy/host tests and RTL format/style checks clean. Evidence and
remaining obligations are recorded in docs/ip/spi-verification.md.
Tiny Icarus behavioral remains blocked by the pre-existing observer/sv2v
defect (routed to the R2 DV owners); Mini smoke synthesis host timeout is
skipped per maintainer decision. Human phase acceptance and SPI-P4/P5
remain outstanding; phase_accepted stays false.
The vendored BIU streams a writeback's W data as soon as the victim
buffer offers it (AXI-legal W-before-AW), while the AW still waits in
awbuf for the serializing 128->64 downsizer to finish the previous
write (the ~200-cycle SDRAM write response latency). The Mini HP
fabric behind the pad is single-outstanding (downsizer + MMIO demux +
target guard, no WID), so the early W beats are absorbed into the
previous write's burst; each write's AW then arrives to find its W
already consumed by the previous write's stream. The cascade persists
until the LSU freezes (its fills block behind the SDRAM write channel,
which is parked waiting for the orphaned write's W data), leaving a
final orphaned AW whose W beats never come: the target guard parks in
WriteStream, the SDRAM core parks in its write-data state and blocks
the pending read fill, and the C906 stalls at the next LSU-serializing
instruction.
Event-level tracing pinned the mechanism: with the guard parked, the
C906 write side is fully idle (victim buffer idle, store buffer idle,
BIU write-selection FIFO empty, zero W beats presented at the 128-bit
port for the wedged write) while the guard and the SDRAM controller
both hold the orphaned write's AW.
The rtl/mini/ip_overrides/aq_biu_write_channel.v override gates the W
stream on the burst's AW having been issued on the pad (pad-issued-AW
vs completed-W-burst order counters), restoring the AW-before-W order
the fabric requires without touching the vendored checkout. The
generator registers the override under the pinned sha256 guard, and
the Makefile stamps it as a dependency.
Evidence: the deterministic wedge payload and the no-fence control run
unbounded (previously wedged at ~22 rounds); hp-smoke-sim and
hp-rtthread-sim pass (SIM_TEST_PASS code=0); hp-linux-sim completes
userspace acceptance (Run /init as init process, HP_LINUX_INIT_PASS,
retroSoC HP Linux ready, HP_LINUX_READY, SIM_TEST_PASS code=0, 1.63 G
emulator cycles, status: passed with no missing markers); pytest
tests/test_hp_platform.py passes 20/20. docs/hp-rv64-validation.md
records the mechanism and the acceptance.
Document the standalone interfaces, timing checker, FIFO pressure cases,
tool-component identity and exact execution commands. Update subsystem
guides and the verification ledger with the matching ICS55/IHP130 evidence.
Keep historical failures and producer identities separate from the new
results. Record the optional PDF-test skip, unconstrained IO boundaries,
deferred full-product regressions and the human phase-acceptance gate.
Validation: 21 local links and the documentation-only post-test delta
checked; git diff --check passed. No generated evidence is committed.
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB
responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session
abort/recovery. Add the handwritten SVH/C register mirror and private
source, credit and GPIO qualification interfaces.
Add independent pin timing and data checks, malformed-waveform negatives,
FIFO stall/resume and phase-safe abort cases. Provide isolated lint,
simulation, compositional formal, synthesis, netlist and observational STA
flows with source-bound artifacts and tool-component fingerprints.
Validation on the reviewed worktree: 2085 pytest tests passed and one
optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and
cover, and ICS55/IHP130 block synthesis and netlist simulation passed.
Formatting, style/readiness, Ruff and regression dry-runs passed.
SPI remains outside product filelists with DMA capability disabled.
SPI-P2/P3 integration, full-product regression closure and physical/IO
qualification remain pending; no phase acceptance or policy change.
Add an isolated SAFE24 QVGA capture, CPU statistics and SDIO save/readback
image with passive transaction observers. Keep ordinary images, production
RTL, public interfaces and dependency versions unchanged.
Retain matched binaries and source-bound stage evidence, distinguish
software comparisons from architectural measurements, and reject invalid
terminal results or incompatible resume inputs. Count SDIO descriptors and
status writebacks separately from pixel payload.
Validation on the final worktree includes 2031 passed / 1 skipped Pytest
tests, C format/policy/host checks, and directed observer tests on Icarus
and Verilator. Selected ICS55 and IHP130 SAFE24 campaigns and compact
backend checks pass; negative STA and warning observations are retained.
Complete P10 acceptance remains pending final regression and human review.
Specification: docs/ip/tiny-soc.md, TINY-R2-P10.
Connect DVP to Tiny DMA2/request 11, IRQ15 and the camera pad/reset lifecycle.
Harden shared capture CDC, frame statistics, per-row size validation and HAL
cleanup while preserving the Mini DMA3 binding and existing register ABI.
Add deterministic capture/recovery firmware, source-bound evidence tooling,
focused RTL/host tests and compact netlist acceptance. Preserve SAFE24,
128 KiB main SRAM, private Crypto storage and the locked dependencies.
Retained validation: focused RTL, host/policy checks, Mini firmware, and
ICS55/IHP130 RECOVERY, QVGA, synthesis and boot/DVP netlist checks pass.
Full-system VGA remains historical; long full Icarus and broad regressions
remain deferred. Global publication/format gaps and negative observational
STA are retained, not reported as passing qualification.
Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
Evidence: docs/ip/tiny-soc-verification.md.
Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md
adds the tiling table (8-bit macro stacking with registered read muxes),
notes the repo-owned functional models versus the vendor collateral in the
locked PDK, and documents the SKY130 byte-mask blocker as the reason that
PDK stays behavioral; hp-rv64-validation.md records the directed-TB,
MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs
generalize the override wording to IHP130/ICS55/GF180. Physical
qualification (Liberty registration, STA, LEC) stays explicitly deferred.
Close out the chapter 3 documentation: hp-platform.md gains the ICG
section (three override points, per-PDK cell table, the ICS55 SE-into-E
note, and the two-state reset rationale), leaving only physical/STA
qualification deferred; hp-rv64-validation.md records the MEM_INTF ICG
results, the five boot testbench modes, and the four SoC-level runs with
the remaining gaps; the two READMEs extend the override inventory to
hart-ID + sysmap + SRAM wrappers + clock-gating cells.
Complete the integration manual chapter 3 cell swap (the ICG half; the
SRAM half landed earlier). Three new reviewed overrides, registered in
generate_openc906.py with sha256 pins on the vendored files and added to
the generated-filelist stamp prerequisites:
- gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM):
pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/
PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell
(sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E
because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with
SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off).
- BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model
stays byte-identical by default; the same four PDK branches substitute
the process cell with the scan input tied off.
The GF180 branch uses a repo-owned icgtp_1 functional model in
rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent)
because the vendor functional model references a UDP latch primitive that
the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor
sdlclkp model through pdk_sky130.fl, following the existing cell pattern.
ASIC CI profiles with PDK_BEHAV unset now compile real clock gating;
PDK_BEHAV=YES profiles are bit-identical.
Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK
cell paths (Icarus adaptation); the five-mode boot testbench suite passes
on top of this change.
Extend the chapter 3 SRAM swap documentation to the ICS55 exact-geometry
macros: hp-platform.md describes the direct-replacement mapping and
gating next to the IHP130 stacking table, hp-rv64-validation.md records
the ICS55 boot-TB, MEM_INTF, and SoC macro-sim evidence along with the
precise remaining gaps (Yosys smoke synth needs Liberty registration for
the new macros; STA/LEC stay deferred), and the two READMEs generalize
the override wording to the PDK-selectable IHP130/ICS55 paths.
Integrate the Tiny RCU, normalized REF24 control, external-input profiles,
single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral
lifecycle control and retained debug behavior. Keep CPU and all 32 main
SRAM macros on SYS and the six private Crypto macros on PCLK.
Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK
operations and focused firmware. Preserve shared-IP defaults and the
ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles.
Use APB/AXI domain bridges and source-owned response holders to preserve
backpressured responses, complete aborted bursts and prevent stale replay.
Verify production DMA source-reset drain and common XPI endpoint reset
with extracted integration bindings and an independent scoreboard.
Add source-bound macro/clock audits, SAFE24 observational STA constraints
and commercial-adapter host checks. No P8 functionality or operating-point
qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md.
Validation: 54 P7 directed tests pass, including both simulators, ten
source-reset ratio runs and two expected-negative drain mutations.
RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs
pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs;
STA remains negative and observational. Source comparison confirms only
the follow-up tests changed after that backend campaign.
Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/
tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility
results and the non-clean full-suite attempt retain their original
attribution. Full Icarus firmware is deferred to final Tiny qualification;
this commit does not constitute human phase acceptance or physical signoff.
Record parent and child process IDs for diagnostics, persist interruption
before cleanup, and ignore repeated termination signals during cleanup.
Close unexpected failures with a terminal result and retain the child's
exit status without treating namespace-local PID absence as completion.
Require a successful terminal run_flow result when checking simulation
logs with an associated result file. Cover repeated cancellation and
reject running, failed or inconsistent terminal records despite PASS text.
This supports the TINY-R2-P7 campaign. Interrupted and timed-out runs remain
non-acceptance evidence; UART output alone cannot qualify a Tiny simulation.
Move the chapter 3 memory swap from deferred to simulation-validated in
docs/ip/hp-platform.md (mechanism, define gating, and the stacking table)
and docs/hp-rv64-validation.md (macro-mode boot TB and SoC macro-sim
evidence, with the remaining synthesis/netlist/STA/LEC gates called out).
Extend the override inventories in rtl/README.md and scripts/README.md to
cover the eight aq_spsram_* wrappers. The chapter 3 ICG replacement and
physical qualification stay explicitly deferred.
Implement the memory replacement required by chapter 3 of the OpenC906
integration manual for the Mini HP core. The eight aq_spsram_* single-port
SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag)
gain reviewed overrides in rtl/mini/ip_overrides/, registered in
scripts/generate_openc906.py with sha256 pins on the vendored files at the
locked revision b0c06eb1.
Each override keeps the upstream behavioral aq_f_spsram_* instance
byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without
PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual
section 3.1.5 (depth stacks with a read-registered bank select, width
stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN
onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off,
matching the tc_sram.sv convention. Committed CI profiles keep
PDK_BEHAV=YES, so their simulation results are unchanged.
The Makefile also lists the new overrides as prerequisites of the
generated-filelist stamp so editing one forces regeneration.
Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus)
and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on
the macro path.
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
- Introduced for formal verification of fault handling in the Tiny R2 P5 architecture.
- Added to test target reset isolation and ensure proper handling of reset signals across multiple targets.
- Created to validate system-level interactions, including CPU and DMA progress during resets.
- Enhanced to include fault counting and master tracking for concurrent fault events.
- Developed to automate testing of concurrency, fault accounting, and retained-image acceptance.
- Updated Python test suite to validate new configurations and ensure proper integration with Tiny R2 P5 architecture.
The Mini HP core is the locked OpenC906 with T-Head XTheadCmo custom-0
dcache maintenance; the former rv64imafdc_zicbom_max VexiiRiscv
configuration survives only as the frozen Std-series generator asset.
Sweep the leftover wording:
- scripts/README.md gains the missing setup_openc906.py and
generate_openc906.py entries (locked source install; sha256-pinned
overrides; single compilation unit below build/).
- configs/README.md and app/README.md describe the OpenC906 core and
XTheadCmo maintenance instead of VexiiRiscv RTL generation and Zicbom.
- The npu-p5-hp-sim help line and the npu_p5_report.py emitted HP
evidence mode now say polling-xtheadcmo, matching the payload's
actual dcache.cva/iva mechanism.
- Updated SRAM instance paths in to reflect new hierarchy.
- Enhanced to include additional source files and updated parameterized tests for SRAM configurations.
- Modified to align with new SRAM structure and added a test for stale macro hierarchy.
- Introduced to validate dual-port local-memory protocol and CPU debug/reset functionality, including comprehensive simulation checks.
- Adjusted slot assignments in to reflect new peripheral mappings.
- Updated to validate new OpenC906 configurations, including generator and profile checks.
- Modified to reference the new Std-series VexiiRiscv generator.
- Changed cache maintenance instructions in to align with C906 specifications.
- Revised assertions in to account for internal unit removals.
- Updated to reflect changes in peripheral interface counts and policies.
- Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
- Implemented tests for WS2812 DMA sessions and refill functionality in .
- Added a new RTL testbench for WS2812 refill functionality in .
- Enhanced AXI4 data crossbar testbench to diagnose MMIO boundaries for the Mini DMA.
- Created a new Python test suite for Tiny R2 P3 to validate firmware warnings and layout placements.
- Updated existing WS2812 tests to parameterize and check for DMA backpressure integration.
- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
maksyuki