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feat: refactor RIB interfaces and update test cases

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- Renamed  and  to  and  respectively across various test files and modules.
- Updated response codes in tests to use new definitions ().
- Added new testbench  to validate RIB to RAM interactions.
- Created  for testing RIBP topology routing.
- Adjusted memory map tests to reflect new interface names.
- Ensured all references to old interface names were replaced in Python test scripts.
- Verified that all test cases pass with the new interface structure.
This commit is contained in:
maksyuki committed 2026-08-04 16:12:22 +08:00
1 parent d51d58dd25
commit a87236ae33
73 files changed
+534 -819
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config/dependencies.lock.json
+1 -1
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@@ -62,7 +62,7 @@
},
"cluster_archinfo": {"url": "https://github.com/retroSoC/archinfo.git", "revision": "d65dd13c83a1176668bf5178004814a1551bf6ba", "destination": "rtl/managed/clusterip/archinfo", "license": "NOASSERTION"},
"cluster_clint": {"url": "https://github.com/retroSoC/clint.git", "revision": "ce49f1a5501c0a9f18c0e3f358417648f3f2fb18", "destination": "rtl/managed/clusterip/clint", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "f666d8f04977157fe282ca9873c45aad6757c37f", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "16ee9a5cfdc1248f35f0993710e3cb89464c19d9", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
"cluster_crc": {"url": "https://github.com/retroSoC/crc.git", "revision": "4654a63d06d487b5b9fe22af228c36c736b90bad", "destination": "rtl/managed/clusterip/crc", "license": "NOASSERTION"},
"cluster_i2c": {"url": "https://github.com/retroSoC/i2c.git", "revision": "73b024547c5cd70fb8bf801cc7757db2536c604f", "destination": "rtl/managed/clusterip/i2c", "license": "NOASSERTION"},
"cluster_i2s": {"url": "https://github.com/retroSoC/i2s.git", "revision": "bd0978e8b45e4cf4c1335a1fa7311385d2a4e805", "destination": "rtl/managed/clusterip/i2s", "license": "NOASSERTION"},
docs/rib-interconnect.md
+23 -25
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@@ -1,27 +1,33 @@
# RIB Family Protocols
retroSoC uses three related protocols. The interface declarations and the
generated address map are the executable source of truth; this document fixes
the ownership, ordering, and adaptation rules at each boundary.
retroSoC uses a scalar peripheral protocol and a native burst interconnect.
The interface declarations and generated address map are the executable source
of truth; this document fixes the ownership, ordering, and adaptation rules at
each boundary.
| Protocol | Interface | Purpose | Transfer shape |
| --- | --- | --- | --- |
| RIBL | `soc_ribl_if` | Legacy SoC master compatibility | One scalar word request and response |
| RIB | `soc_rib_if` | Native retroSoC interconnect | Split command, write-data, and response channels |
| RIBP | ClusterIP `ribp_if` | Peripheral and IP compatibility | One scalar word request and response |
| RIBP | Common `ribp_if` | Scalar core and peripheral compatibility | One scalar word request and response |
| RIB | `rib_if` | Native retroSoC interconnect | Split command, write-data, and response channels |
## RIBL
## RIBP
RIBL is the SoC-owned scalar compatibility protocol. A master presents
RIBP is the scalar Common protocol used at every core and peripheral boundary.
A master presents
`valid`, `addr`, `wdata`, and `wstrb`; a slave completes the request with
`ready`, `rdata`, and `resp_err`. `wstrb == 0` denotes a read. There is no
burst metadata, response code, ID, reordering, or more than one transaction
in flight through the RIBL adapter.
in flight through the RIBP adapter.
`soc_ribl2rib` converts RIBL requests to native `INCR1` RIB transactions. It
maps the terminal RIB response to the RIBL `ready` handshake and propagates
`ribp2rib` converts RIBP requests to native `INCR1` RIB transactions. It
maps the terminal RIB response to the RIBP `ready` handshake and propagates
the RIB error flag as `resp_err`.
Leaf RIBP IP currently responds with `resp_err == 0`. RIBP multiplexers,
register slices, and bypass paths preserve a selected downstream error. The
APB bridge maps `PSLVERR` directly to `resp_err`; this is the only current
RIBP error producer.
## RIB
RIB is the retroSoC Interconnect Bus. Version 1 has independent command,
@@ -39,7 +45,7 @@ transaction per master.
RIB has no IDs, narrow read beats, wrapping bursts, reordering, or multiple
outstanding transactions. `BURSTERR` reports an unsupported length, bad
alignment, unsupported target, or malformed write-last sequence. The response
code definitions are in `soc_rib_defs.svh`.
code definitions are in `rib_defs.svh`.
The generated address map is the capability source of truth. Register and APB
regions remain `INCR1` only. SRAM, SDRAM, PSRAM, flash/XPI, and SPI-SD memory
@@ -47,25 +53,17 @@ windows accept `INCR4`; the interconnect validates both the first and last
address before forwarding a command. DMA falls back to `INCR1` unless both
endpoints, including their fourth words, support `INCR4`.
## RIBP
RIBP is the scalar ClusterIP protocol defined by `ribp_if`. It transfers
`addr`, `wdata`, and `wstrb` with `valid/ready`; `wstrb == 0` denotes a read
and `rdata` is returned with the completing `ready` handshake. RIBP carries no
burst length, beat index, terminal marker, response code, or error signal.
`soc_rib2ribp` serializes legal RIB beats into RIBP accesses and reconstructs
ordered RIB responses. Target-side error sideband inputs are converted to RIB
response status at this boundary. `ribp2rib` is the inverse compatibility
adapter for a scalar RIBP initiator that must access a native RIB target.
`rib2ribp` serializes legal RIB beats into RIBP accesses and reconstructs
ordered RIB responses. An asserted RIBP `resp_err` is mapped to native RIB
`SLVERR`; RIBP intentionally carries no response-code field.
## Targets and Performance
Management and current user cores use RIBL through the SoC adapters. Future
Management and current user cores use RIBP through the SoC adapters. Future
user cores can select native RIB in `user_extensions.json`. DMA is a native
RIB master and uses the common four-entry FIFO for each chunk.
`soc_rib2ram` is the native RIB SRAM target. It pipelines synchronous reads
`rib2ram` is the native RIB SRAM target. It pipelines synchronous reads
and uses the Common two-entry spill register for response backpressure. The
Common repository owns direct verification of that utility; retroSoC verifies
the RIB target behavior and its integration contract.
rtl/ip/ribp/interconnect/ahbl2ribp.sv
-172
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@@ -1,172 +0,0 @@
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module ahbl2ribp (
ahbl_if.slave ahbl,
ribp_if.master ribp
);
localparam AHBL_TRANS_IDLE = 2'b00;
localparam AHBL_TRANS_BUSY = 2'b01;
localparam AHBL_TRANS_NSEQ = 2'b10;
localparam AHBL_TRANS_SEQ = 2'b11;
localparam AHBL_SIZE_BYTE = 3'b000;
localparam AHBL_SIZE_HWRD = 3'b001;
localparam AHBL_SIZE_WORD = 3'b010;
localparam AHBL_RESP_OKAY = 1'b0;
localparam AHBL_RESP_EROR = 1'b1;
localparam STATE_IDLE = 2'b00;
localparam STATE_DATA = 2'b01;
localparam STATE_WAIT = 2'b10;
logic [1:0] s_fsm_d, s_fsm_q;
// req
logic [31:0] s_haddr_d, s_haddr_q;
logic s_hwrite_d, s_hwrite_q;
logic [2:0] s_hsize_d, s_hsize_q;
// ahbl if
// NOTE: need to gurantee `ahbl.hready` and `ahbl.hrdata` sampled in same cycle
assign ahbl.hready = (s_fsm_q == STATE_IDLE) || ribp.ready;
assign ahbl.hresp = AHBL_RESP_OKAY;
assign ahbl.hrdata = ribp.rdata;
// ribp if
assign ribp.valid = s_fsm_q != STATE_IDLE;
assign ribp.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
ribp.wstrb = '0;
ribp.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'b00: begin
ribp.wstrb = 4'b0001;
ribp.wdata = {24'b0, ahbl.hwdata[7:0]};
end
2'b01: begin
ribp.wstrb = 4'b0010;
ribp.wdata = {16'b0, ahbl.hwdata[7:0], 8'b0};
end
2'b10: begin
ribp.wstrb = 4'b0100;
ribp.wdata = {8'b0, ahbl.hwdata[7:0], 16'b0};
end
2'b11: begin
ribp.wstrb = 4'b1000;
ribp.wdata = {ahbl.hwdata[7:0], 24'b0};
end
default: begin
ribp.wstrb = 4'b0001;
ribp.wdata = {24'b0, ahbl.hwdata[7:0]};
end
endcase
end
AHBL_SIZE_HWRD: begin
unique case (s_haddr_q[1])
1'b0: begin
ribp.wstrb = 4'b0011;
ribp.wdata = {16'b0, ahbl.hwdata[15:0]};
end
1'b1: begin
ribp.wstrb = 4'b1100;
ribp.wdata = {ahbl.hwdata[15:0], 16'd0};
end
endcase
end
AHBL_SIZE_WORD: begin
ribp.wstrb = 4'b1111;
ribp.wdata = ahbl.hwdata;
end
default: begin
ribp.wstrb = 4'b1111;
ribp.wdata = ahbl.hwdata;
end
endcase
end
end
// ahb.hready,
always_comb begin
s_fsm_d = s_fsm_q;
s_haddr_d = s_haddr_q;
s_hwrite_d = s_hwrite_q;
s_hsize_d = s_hsize_q;
unique case (s_fsm_q)
STATE_IDLE: begin
// just for no-burst ahbl
if (ahbl.htrans == AHBL_TRANS_NSEQ && ahbl.hready) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
s_hsize_d = ahbl.hsize;
end
end
STATE_DATA: begin
if (~ribp.ready) s_fsm_d = STATE_WAIT;
// ribp.ready == 1'b1
else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
s_hsize_d = ahbl.hsize;
end else s_fsm_d = STATE_IDLE;
end
STATE_WAIT: begin
if (ribp.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
s_hwrite_d = ahbl.hwrite;
s_hsize_d = ahbl.hsize;
end else s_fsm_d = STATE_IDLE;
end
end
default: begin
s_fsm_d = STATE_IDLE;
end
endcase
end
dffr #(2) u_fsm_dffr (
ahbl.hclk,
ahbl.hresetn,
s_fsm_d,
s_fsm_q
);
dffr #(32) u_haddr_dffr (
ahbl.hclk,
ahbl.hresetn,
s_haddr_d,
s_haddr_q
);
dffr #(1) u_hwrite_dffr (
ahbl.hclk,
ahbl.hresetn,
s_hwrite_d,
s_hwrite_q
);
dffr #(3) u_hsize_dffr (
ahbl.hclk,
ahbl.hresetn,
s_hsize_d,
s_hsize_q
);
endmodule
rtl/ip/ribp/interconnect/axi4l2ribp.sv
+24 -2
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@@ -41,6 +41,8 @@ module axi4l2ribp (
localparam [1:0] WR_DATA = 2'd1;
localparam [1:0] WR_WAIT = 2'd2;
localparam [1:0] WR_RESP = 2'd3;
localparam [1:0] AXI_RESP_OKAY = 2'b00;
localparam [1:0] AXI_RESP_SLVERR = 2'b10;
logic [1:0] s_rd_fsm_d, s_rd_fsm_q;
logic [1:0] s_wr_fsm_d, s_wr_fsm_q;
@@ -49,6 +51,8 @@ module axi4l2ribp (
logic [31:0] s_rdata_d, s_rdata_q;
logic [31:0] s_wdata_d, s_wdata_q;
logic [3:0] s_wstrb_d, s_wstrb_q;
logic [1:0] s_rresp_d, s_rresp_q;
logic [1:0] s_bresp_d, s_bresp_q;
logic s_rd_req, s_wr_req;
always_comb begin
@@ -125,6 +129,15 @@ module axi4l2ribp (
s_rdata_q
);
assign s_rresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
dffer #(2) u_rresp_dffer (
aclk_i,
aresetn_i,
s_rd_fsm_q == RD_DATA && ribp.ready,
s_rresp_d,
s_rresp_q
);
assign s_wdata_d = wdata_i;
dffer #(32) u_wdata_dffer (
aclk_i,
@@ -143,16 +156,25 @@ module axi4l2ribp (
s_wstrb_q
);
assign s_bresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
dffer #(2) u_bresp_dffer (
aclk_i,
aresetn_i,
s_wr_fsm_q == WR_WAIT && ribp.ready,
s_bresp_d,
s_bresp_q
);
// axil
assign arready_o = s_rd_fsm_q == RD_IDLE && arvalid_i;
assign rvalid_o = s_rd_fsm_q == RD_WAIT;
assign rresp_o = '0;
assign rresp_o = s_rresp_q;
assign rdata_o = s_rdata_q;
assign awready_o = s_wr_fsm_q == WR_IDLE && awvalid_i;
assign wready_o = s_wr_fsm_q == WR_DATA && wvalid_i;
assign bvalid_o = s_wr_fsm_q == WR_RESP;
assign bresp_o = '0;
assign bresp_o = s_bresp_q;
assign s_rd_req = (s_rd_fsm_q == RD_DATA || s_rd_fsm_q == RD_WAIT);
assign s_wr_req = s_wr_fsm_q == WR_WAIT;
rtl/ip/ribp/interconnect/ribp2apb.sv
+1 -2
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@@ -15,7 +15,6 @@ module ribp2apb (
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
output logic resp_err_o,
`include "soc_apb_ports.svh"
// verilog_format: on
);
@@ -66,7 +65,7 @@ module ribp2apb (
assign ribp.ready = ribp.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
assign ribp.rdata = {32{ribp.ready}} & s_rd_data;
assign resp_err_o = ribp.ready && s_xfer_error;
assign ribp.resp_err = ribp.ready && s_xfer_error;
// Capture slave-select one-hot at FSM_SETP for cleaner response mux.
`include "soc_apb_select_routes.svh"
rtl/ip/ribp/interconnect/ribp_regslice.sv
+14
View File
@@ -28,6 +28,7 @@ module ribp_regslice (
logic [3:0] s_ribp_mst_wstrb_d, s_ribp_mst_wstrb_q;
logic [31:0] s_ribp_mst_rdata_d, s_ribp_mst_rdata_q;
logic s_ribp_mst_ready_d, s_ribp_mst_ready_q;
logic s_ribp_mst_resp_err_d, s_ribp_mst_resp_err_q;
// ribp mst if
assign ribp_mst.valid = s_ribp_mst_valid_q;
assign ribp_mst.addr = s_ribp_mst_addr_q;
@@ -43,8 +44,10 @@ module ribp_regslice (
s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
s_ribp_mst_ready_d = s_ribp_mst_ready_q;
s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
s_ribp_mst_resp_err_d = s_ribp_mst_resp_err_q;
ribp_slv.ready = '0;
ribp_slv.rdata = '0;
ribp_slv.resp_err = 1'b0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (ribp_slv.valid) begin
@@ -61,12 +64,14 @@ module ribp_regslice (
s_ribp_mst_valid_d = 1'b0;
s_ribp_mst_ready_d = ribp_mst.ready;
s_ribp_mst_rdata_d = ribp_mst.rdata;
s_ribp_mst_resp_err_d = ribp_mst.resp_err;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
ribp_slv.ready = s_ribp_mst_ready_q;
ribp_slv.rdata = s_ribp_mst_rdata_q;
ribp_slv.resp_err = s_ribp_mst_resp_err_q;
end
default: begin
s_fsm_d = s_fsm_q;
@@ -76,8 +81,10 @@ module ribp_regslice (
s_ribp_mst_wstrb_d = s_ribp_mst_wstrb_q;
s_ribp_mst_ready_d = s_ribp_mst_ready_q;
s_ribp_mst_rdata_d = s_ribp_mst_rdata_q;
s_ribp_mst_resp_err_d = s_ribp_mst_resp_err_q;
ribp_slv.ready = '0;
ribp_slv.rdata = '0;
ribp_slv.resp_err = 1'b0;
end
endcase
end
@@ -133,4 +140,11 @@ module ribp_regslice (
s_ribp_mst_ready_q
);
dffr #(1) u_ribp_mst_resp_err_dffr (
clk_i,
rst_n_i,
s_ribp_mst_resp_err_d,
s_ribp_mst_resp_err_q
);
endmodule
rtl/ip/ribp/memory/opipsram.sv
+1
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@@ -47,6 +47,7 @@ module ribp_opipsram (
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
assign ribp.resp_err = 1'b0;
// psram
assign psram.sck_o = '0;
assign psram.ce_o = '0;
rtl/ip/ribp/memory/psram.sv
+1
View File
@@ -128,6 +128,7 @@ module ribp_psram (
assign s_mem_sel = `SOC_ADDR_IS_PSRAM(ribp.addr);
assign s_cfg_reg_sel = `SOC_ADDR_IS_RIBP_PSRAM(ribp.addr);
assign ribp.ready = s_mem_sel ? s_mem_ready : 1'b1;
assign ribp.resp_err = 1'b0;
always_comb begin
ribp.rdata = '0;
if (s_mem_sel) begin
rtl/ip/ribp/memory/sdram.sv
+2
View File
@@ -76,6 +76,8 @@ module ribp_sdram (
// verilog_format: off
assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mem_ribp_if.valid & u_mem_ribp_if.ready);
assign ribp.resp_err = (u_reg_ribp_if.valid & u_reg_ribp_if.ready & u_reg_ribp_if.resp_err) |
(u_mem_ribp_if.valid & u_mem_ribp_if.ready & u_mem_ribp_if.resp_err);
assign ribp.rdata = ({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mem_ribp_if.valid & u_mem_ribp_if.ready)}} & u_mem_ribp_if.rdata);
rtl/ip/ribp/memory/sdram_core.sv
+1
View File
@@ -143,6 +143,7 @@ module sdram_core (
// ribp
assign ribp.ready = s_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_rdata_q;
// sdram
assign sdram.clk_o = sdram_clk_i;
rtl/ip/ribp/memory/sdram_reg.sv
+1
View File
@@ -39,6 +39,7 @@ module sdram_reg (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign clkdiv_o = s_sdram_clkdiv_q;
rtl/ip/ribp/multimedia/dvp.sv
+1
View File
@@ -57,6 +57,7 @@ module ribp_dvp (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && ribp.wstrb[0];
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
rtl/ip/ribp/peripheral/clint.sv
+1
View File
@@ -60,6 +60,7 @@ module ribp_clint (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// pipelined 64-bit magnitude compare (registered output)
rtl/ip/ribp/peripheral/dma.sv
+2 -1
View File
@@ -45,7 +45,7 @@ module ribp_dma (
output logic dma_xfer_done_o,
dma_hw_trg_if.dut hw_trg,
ribp_if.slave ribp,
soc_rib_if.master rib
rib_if.master rib
// verilog_format: on
);
@@ -81,6 +81,7 @@ module ribp_dma (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign dma_xfer_done_o = s_dma_status_q;
rtl/ip/ribp/peripheral/dma_core.sv
+4 -4
View File
@@ -9,7 +9,7 @@
// See the Mulan PSL v2 for more details.
`include "mmap_define.svh"
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
module dma_core (
// verilog_format: off
@@ -30,7 +30,7 @@ module dma_core (
output logic [31:0] error_addr_o,
output logic [1:0] fsm_o,
dma_hw_trg_if.dut hw_trg,
soc_rib_if.master rib
rib_if.master rib
// verilog_format: on
);
@@ -78,7 +78,7 @@ module dma_core (
`SOC_ADDR_SUPPORTS_INCR4(s_dst_addr_q) &&
`SOC_ADDR_SUPPORTS_INCR4(s_dst_addr_q + 32'd12);
// verilog_format: on
assign s_chunk_len = s_use_burst ? `SOC_RIB_LEN_INCR4 : `SOC_RIB_LEN_INCR1;
assign s_chunk_len = s_use_burst ? `RIB_LEN_INCR4 : `RIB_LEN_INCR1;
assign s_chunk_words = s_use_burst ? 32'd4 : 32'd1;
always_comb begin
@@ -148,7 +148,7 @@ module dma_core (
s_wr_beat_d = s_wr_beat_q;
done_o = 1'b0;
error_o = 1'b0;
error_code_o = `SOC_RIB_RESP_OK;
error_code_o = `RIB_RESP_OK;
error_addr_o = s_src_addr_q;
if (reset_i) begin
rtl/ip/ribp/peripheral/gpio.sv
+1
View File
@@ -135,6 +135,7 @@ module ribp_gpio (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// gpio
assign gpio.cs_o = s_gpio_cs_q; // 1: CMOS 0: SCHMI
rtl/ip/ribp/peripheral/sysctrl.sv
+8 -7
View File
@@ -10,7 +10,7 @@
`include "user_extensions.svh"
`include "mmap_define.svh"
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
interface sysctrl_if ();
logic [`USER_CORESEL_WIDTH-1:0] core_sel_o;
@@ -172,6 +172,7 @@ module ribp_sysctrl (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
@@ -469,13 +470,13 @@ module ribp_sysctrl (
if (~s_fault_pending_q || s_fault_status_clear) begin
s_fault_write_d = |fault_wstrb_i;
s_fault_detail_d = |sysctrl.fault_code_i ? sysctrl.fault_code_i :
sysctrl.fault_access_i ? `SOC_RIB_RESP_PROTERR :
fault_reserved_i ? `SOC_RIB_RESP_RESERVED : `SOC_RIB_RESP_DECERR;
sysctrl.fault_access_i ? `RIB_RESP_PROTERR :
fault_reserved_i ? `RIB_RESP_RESERVED : `RIB_RESP_DECERR;
unique case (s_fault_detail_d)
`SOC_RIB_RESP_RESERVED: s_fault_reason_d = 3'd2;
`SOC_RIB_RESP_PROTERR: s_fault_reason_d = 3'd3;
`SOC_RIB_RESP_SLVERR: s_fault_reason_d = 3'd4;
`SOC_RIB_RESP_TIMEOUT: s_fault_reason_d = 3'd5;
`RIB_RESP_RESERVED: s_fault_reason_d = 3'd2;
`RIB_RESP_PROTERR: s_fault_reason_d = 3'd3;
`RIB_RESP_SLVERR: s_fault_reason_d = 3'd4;
`RIB_RESP_TIMEOUT: s_fault_reason_d = 3'd5;
default: s_fault_reason_d = 3'd1;
endcase
s_fault_addr_d = fault_addr_i;
rtl/ip/ribp/peripheral/timer.sv
+1
View File
@@ -74,6 +74,7 @@ module ribp_timer (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign s_bit_en = s_tim_cfg_q[0];
rtl/ip/ribp/serial/i2c.sv
+1
View File
@@ -66,6 +66,7 @@ module ribp_i2c (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
rtl/ip/ribp/serial/i2s_reg.sv
+1
View File
@@ -57,6 +57,7 @@ module i2s_reg (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign mode_o = s_i2s_mode_q;
rtl/ip/ribp/serial/onewire.sv
+1
View File
@@ -64,6 +64,7 @@ module ribp_onewire (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
rtl/ip/ribp/serial/uart.sv
+1
View File
@@ -72,6 +72,7 @@ module ribp_uart (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
assign uart.tx_o = r_send_pattern[0];
rtl/ip/ribp/storage/sdio.sv
+1
View File
@@ -45,6 +45,7 @@ module ribp_sdio (
// ribp
assign ribp.rdata = '0;
assign ribp.ready = '0;
assign ribp.resp_err = 1'b0;
// sdio
assign sdio.sck_o = '0;
assign sdio.cmd_oe_o = '0;
rtl/ip/ribp/storage/spisd.sv
+4
View File
@@ -59,6 +59,8 @@ module ribp_spisd (
assign ribp.ready = s_cfg_reg_sel ? u_cfg_ribp_if.ready : u_cache_mem_ribp_if.ready;
assign ribp.rdata = s_cfg_reg_sel ? u_cfg_ribp_if.rdata : u_cache_mem_ribp_if.rdata;
assign ribp.resp_err = s_cfg_reg_sel ? u_cfg_ribp_if.resp_err :
u_cache_mem_ribp_if.resp_err;
// verilog_format: on
spisd_reg u_spisd_reg (
@@ -81,8 +83,10 @@ module ribp_spisd (
assign u_cache_byp_ribp_if.ready = s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_byp_ribp_if.rdata = s_mode ? u_cache_ribp_if.rdata : '0;
assign u_cache_byp_ribp_if.resp_err = s_mode ? u_cache_ribp_if.resp_err : 1'b0;
assign u_cache_mem_ribp_if.ready = ~s_mode ? u_cache_ribp_if.ready : '0;
assign u_cache_mem_ribp_if.rdata = ~s_mode ? u_cache_ribp_if.rdata : '0;
assign u_cache_mem_ribp_if.resp_err = ~s_mode ? u_cache_ribp_if.resp_err : 1'b0;
spisd_cache u_spisd_cache (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
rtl/ip/ribp/storage/spisd_cache.sv
+1
View File
@@ -80,6 +80,7 @@ module spisd_cache (
sd_addr_o = '0;
// mem_if
ribp.ready = '0;
ribp.resp_err = 1'b0;
// wr sync
wr_sync_done_o = '0;
unique case (s_cache_fsm_q)
rtl/ip/ribp/storage/spisd_reg.sv
+1
View File
@@ -59,6 +59,7 @@ module spisd_reg (
assign s_rd_byp = s_ribp_rd_hdshk && ribp.addr[7:0] == `RIBP_SPISD_RXDATA;
assign ribp.ready = (s_wr_byp || s_rd_byp) ? byp_rib.ready : s_ribp_ready_q;
assign ribp.rdata = (s_wr_byp || s_rd_byp) ? byp_rib.rdata : s_ribp_rdata_q;
assign ribp.resp_err = (s_wr_byp || s_rd_byp) ? byp_rib.resp_err : 1'b0;
// common
assign mode_o = s_spisd_mode_q;
assign clkdiv_o = s_spisd_clkdiv_q;
rtl/ip/ribp/storage/xpi.sv
+2
View File
@@ -121,6 +121,8 @@ module ribp_xpi (
// verilog_format: off
assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) |
(u_mm_ribp_if.valid & u_mm_ribp_if.ready);
assign ribp.resp_err = (u_reg_ribp_if.valid & u_reg_ribp_if.ready & u_reg_ribp_if.resp_err) |
(u_mm_ribp_if.valid & u_mm_ribp_if.ready & u_mm_ribp_if.resp_err);
assign ribp.rdata = ({32{(u_reg_ribp_if.valid & u_reg_ribp_if.ready)}} & u_reg_ribp_if.rdata) |
({32{(u_mm_ribp_if.valid & u_mm_ribp_if.ready)}} & u_mm_ribp_if.rdata);
rtl/ip/ribp/storage/xpi_mm.sv
+1
View File
@@ -66,6 +66,7 @@ module xpi_mm (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// ribp rd
always_comb begin
rtl/ip/ribp/storage/xpi_reg.sv
+1
View File
@@ -193,6 +193,7 @@ module xpi_reg (
assign s_ribp_wr_hdshk = ribp.valid && (~s_ribp_ready_q) && (|ribp.wstrb);
assign s_ribp_rd_hdshk = ribp.valid && (~s_ribp_ready_q) && (~(|ribp.wstrb));
assign ribp.ready = s_ribp_ready_q;
assign ribp.resp_err = 1'b0;
assign ribp.rdata = s_ribp_rdata_q;
// reg
assign xpi_accmd_o = s_xpi_accmd_q;
rtl/mini/dv/sva/soc_protocol_sva.sv → rtl/mini/dv/sva/rib_protocol_sva.sv
+6 -6
View File
@@ -11,7 +11,7 @@
`ifndef SV_ASSRT_DISABLE
`ifndef SYNTHESIS
module soc_bus_sva (
module rib_bus_sva (
input logic clk_i,
input logic rst_n_i,
input logic fault_cmd_accept_i,
@@ -40,7 +40,7 @@ module soc_bus_sva (
endmodule
bind bus soc_bus_sva u_soc_bus_sva (
bind bus rib_bus_sva u_rib_bus_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.fault_cmd_accept_i(s_fault_cmd_hdshk),
@@ -49,12 +49,12 @@ bind bus soc_bus_sva u_soc_bus_sva (
.access_denied_i (s_access_denied),
.cmd_accepted_i (s_cmd_accepted_q),
.arb_owner_i (s_mstr_id_q),
.mgmt_valid_i (mgmt_ribl.valid),
.mgmt_valid_i (mgmt_ribp.valid),
.user_valid_i (user_rib.cmd_valid),
.dma_valid_i (dma_rib.cmd_valid)
);
module soc_rib2apb_sva #(
module rib2apb_sva #(
parameter int NSLV = 1
) (
input logic clk_i,
@@ -72,9 +72,9 @@ module soc_rib2apb_sva #(
endmodule
bind ribp2apb soc_rib2apb_sva #(
bind ribp2apb rib2apb_sva #(
.NSLV(NSLV)
) u_soc_rib2apb_sva (
) u_rib2apb_sva (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.psel_comb_i (s_psel_comb),
rtl/mini/filelist/commonip.fl
+1 -2
View File
@@ -3,8 +3,7 @@
/clusterip/common/rtl/interface/ahbl_if.sv
/clusterip/common/rtl/interface/ribp_if.sv
/clusterip/common/rtl/interface/ram_if.sv
/top/soc_ribl_if.sv
/top/soc_rib_if.sv
/top/rib_if.sv
/clusterip/common/rtl/utils/register.sv
/top/soc_common_fifo.sv
/clusterip/common/rtl/utils/spill_register.sv
rtl/mini/filelist/ip.fl
+1 -2
View File
@@ -41,8 +41,7 @@
/ip/ribp/serial/uart.sv
/ip/ribp/peripheral/gpio.sv
/ip/ribp/interconnect/ribp2apb.sv
/ip/ribp/interconnect/ahbl2ribp.sv
/top/ahbl2soc_ribl.sv
/top/ahbl2ribp.sv
/ip/ribp/interconnect/axi4l2ribp.sv
/ip/ribp/util/async_fifo.sv
/ip/ribp/interconnect/ribp_regslice.sv
rtl/mini/filelist/top.fl
+4 -5
View File
@@ -1,10 +1,9 @@
/top/apb4_if_bridge.sv
/top/gpio_pad_bridge.sv
/top/soc_ribl2rib.sv
/top/ribp2rib.sv
/top/soc_rib2ribp.sv
/top/soc_rib_error_slave.sv
/top/soc_rib2ram.sv
/top/rib2ribp.sv
/top/rib_error_slave.sv
/top/rib2ram.sv
/top/core_wrapper.sv
/top/retrosoc.sv
/top/retrosoc_asic.sv
@@ -19,4 +18,4 @@
/top/user_ip_design_template.sv
/top/user_ip_top.sv
/top/user_ip_wrapper.sv
/sva/soc_protocol_sva.sv
/sva/rib_protocol_sva.sv
rtl/mini/formal/bus_formal.sv
+15 -15
View File
@@ -30,10 +30,10 @@ module bus_formal_design (
output logic terminal_rsp
);
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if mgmt_ribp ();
rib_if user_rib ();
rib_if dma_rib ();
rib_if rib ();
ribp_if apb_ribp ();
(* anyseq *)logic f_mgmt_valid;
@@ -71,10 +71,10 @@ module bus_formal_design (
logic [ 2:0] fault_code;
logic user_idle;
assign mgmt_ribl.valid = f_mgmt_valid;
assign mgmt_ribl.addr = f_mgmt_addr;
assign mgmt_ribl.wdata = f_mgmt_wdata;
assign mgmt_ribl.wstrb = f_mgmt_wstrb;
assign mgmt_ribp.valid = f_mgmt_valid;
assign mgmt_ribp.addr = f_mgmt_addr;
assign mgmt_ribp.wdata = f_mgmt_wdata;
assign mgmt_ribp.wstrb = f_mgmt_wstrb;
assign user_rib.cmd_valid = f_user_cmd_valid;
assign user_rib.cmd_addr = f_user_cmd_addr;
@@ -101,7 +101,7 @@ module bus_formal_design (
assign rib.rsp_valid = target_active_q && (~target_write_q || target_write_done_q);
assign rib.rdata = 32'hCAFE_0000 | {30'd0, target_beat_q};
assign rib.resp_err = 1'b0;
assign rib.resp_code = `SOC_RIB_RESP_OK;
assign rib.resp_code = `RIB_RESP_OK;
assign rib.rsp_beat = target_beat_q;
assign rib.rsp_last = target_write_q || (target_beat_q == target_len_q);
@@ -140,11 +140,12 @@ module bus_formal_design (
assign apb_ribp.ready = apb_ribp.valid;
assign apb_ribp.rdata = 32'h1234_5678;
assign apb_ribp.resp_err = 1'b0;
assign mgmt_valid = mgmt_ribl.valid;
assign mgmt_addr = mgmt_ribl.addr;
assign mgmt_wstrb = mgmt_ribl.wstrb;
assign mgmt_ready = mgmt_ribl.ready;
assign mgmt_valid = mgmt_ribp.valid;
assign mgmt_addr = mgmt_ribp.addr;
assign mgmt_wstrb = mgmt_ribp.wstrb;
assign mgmt_ready = mgmt_ribp.ready;
assign user_cmd_valid = user_rib.cmd_valid;
assign user_cmd_ready = user_rib.cmd_ready;
assign user_cmd_addr = user_rib.cmd_addr;
@@ -162,14 +163,13 @@ module bus_formal_design (
bus u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_ribl (mgmt_ribl),
.mgmt_ribp (mgmt_ribp),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_idle),
.rib (rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid),
rtl/mini/formal/generate_formal_filelist.py
+7 -8
View File
@@ -31,25 +31,24 @@ def source_files(target: str) -> list[Path]:
COMMON_RTL / "interface/ribp_if.sv",
COMMON_RTL / "interface/ram_if.sv",
COMMON_RTL / "utils/register.sv",
TOP / "soc_ribl_if.sv",
TOP / "soc_rib_if.sv",
TOP / "rib_if.sv",
]
if target == "bus":
return [
*common,
COMMON_RTL / "utils/spill_register.sv",
TOP / "soc_ribl2rib.sv",
TOP / "soc_rib2ribp.sv",
TOP / "soc_rib_error_slave.sv",
TOP / "soc_rib2ram.sv",
TOP / "ribp2rib.sv",
TOP / "rib2ribp.sv",
TOP / "rib_error_slave.sv",
TOP / "rib2ram.sv",
TOP / "bus.sv",
SCRIPT_DIR / "bus_formal.sv",
]
if target == "rib_adapter":
return [
*common,
TOP / "soc_ribl2rib.sv",
TOP / "soc_rib2ribp.sv",
TOP / "ribp2rib.sv",
TOP / "rib2ribp.sv",
SCRIPT_DIR / "rib_adapter_formal.sv",
]
if target == "ribp2apb":
rtl/mini/formal/rib_adapter_formal.sv
+24 -18
View File
@@ -18,16 +18,19 @@ module rib_adapter_formal_design (
output logic rsp_valid,
output logic rsp_ready,
output logic [31:0] rsp_rdata,
output logic rsp_error,
output logic [ 2:0] rsp_code,
output logic [ 1:0] rsp_beat,
output logic rsp_last,
output logic ribp_valid,
output logic ribp_ready,
output logic ribp_resp_err,
output logic [31:0] ribp_addr,
output logic [31:0] ribp_wdata,
output logic [ 3:0] ribp_wstrb,
output logic source_valid,
output logic source_ready,
output logic source_resp_err,
output logic [31:0] source_addr,
output logic [ 3:0] source_wstrb,
output logic adapted_cmd_valid,
@@ -38,13 +41,14 @@ module rib_adapter_formal_design (
output logic adapted_w_ready,
output logic [31:0] adapted_wdata,
output logic [ 3:0] adapted_wstrb,
output logic adapted_wlast
output logic adapted_wlast,
output logic adapted_rsp_error
);
soc_rib_if rib_source ();
rib_if rib_source ();
ribp_if ribp_target ();
soc_ribl_if ribl_source ();
soc_rib_if rib_target ();
ribp_if ribp_source ();
rib_if rib_target ();
(* anyseq *)logic f_cmd_valid;
(* anyseq *)logic [31:0] f_cmd_addr;
@@ -58,7 +62,6 @@ module rib_adapter_formal_design (
(* anyseq *)logic f_ribp_ready;
(* anyseq *)logic [31:0] f_ribp_rdata;
(* anyseq *)logic f_ribp_error;
(* anyseq *)logic [ 2:0] f_ribp_code;
(* anyseq *)logic f_source_valid;
(* anyseq *)logic [31:0] f_source_addr;
@@ -82,20 +85,19 @@ module rib_adapter_formal_design (
assign rib_source.rsp_ready = f_rsp_ready;
assign ribp_target.ready = f_ribp_ready;
assign ribp_target.rdata = f_ribp_rdata;
assign ribp_target.resp_err = f_ribp_error;
soc_rib2ribp u_rib2ribp (
rib2ribp u_rib2ribp (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribp_resp_err_i (f_ribp_error),
.ribp_resp_code_i(f_ribp_code),
.rib (rib_source),
.ribp (ribp_target)
);
assign ribl_source.valid = f_source_valid;
assign ribl_source.addr = f_source_addr;
assign ribl_source.wdata = f_source_wdata;
assign ribl_source.wstrb = f_source_wstrb;
assign ribp_source.valid = f_source_valid;
assign ribp_source.addr = f_source_addr;
assign ribp_source.wdata = f_source_wdata;
assign ribp_source.wstrb = f_source_wstrb;
assign rib_target.cmd_ready = f_target_cmd_ready;
assign rib_target.w_ready = f_target_w_ready;
assign rib_target.rsp_valid = f_target_rsp_valid;
@@ -105,10 +107,10 @@ module rib_adapter_formal_design (
assign rib_target.rsp_beat = '0;
assign rib_target.rsp_last = 1'b1;
soc_ribl2rib u_ribl2rib (
ribp2rib u_ribp2rib (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribl (ribl_source),
.ribp (ribp_source),
.rib (rib_target)
);
@@ -125,19 +127,22 @@ module rib_adapter_formal_design (
assign rsp_valid = rib_source.rsp_valid;
assign rsp_ready = rib_source.rsp_ready;
assign rsp_rdata = rib_source.rdata;
assign rsp_error = rib_source.resp_err;
assign rsp_code = rib_source.resp_code;
assign rsp_beat = rib_source.rsp_beat;
assign rsp_last = rib_source.rsp_last;
assign ribp_valid = ribp_target.valid;
assign ribp_ready = ribp_target.ready;
assign ribp_resp_err = ribp_target.resp_err;
assign ribp_addr = ribp_target.addr;
assign ribp_wdata = ribp_target.wdata;
assign ribp_wstrb = ribp_target.wstrb;
assign source_valid = ribl_source.valid;
assign source_ready = ribl_source.ready;
assign source_addr = ribl_source.addr;
assign source_wstrb = ribl_source.wstrb;
assign source_valid = ribp_source.valid;
assign source_ready = ribp_source.ready;
assign source_resp_err = ribp_source.resp_err;
assign source_addr = ribp_source.addr;
assign source_wstrb = ribp_source.wstrb;
assign adapted_cmd_valid = rib_target.cmd_valid;
assign adapted_cmd_ready = rib_target.cmd_ready;
assign adapted_cmd_addr = rib_target.cmd_addr;
@@ -147,6 +152,7 @@ module rib_adapter_formal_design (
assign adapted_wdata = rib_target.wdata;
assign adapted_wstrb = rib_target.wstrb;
assign adapted_wlast = rib_target.wlast;
assign adapted_rsp_error = rib_target.resp_err;
initial begin
rst_n_i = 1'b0;
rtl/mini/formal/rib_adapter_formal_props.sv
+11 -4
View File
@@ -2,6 +2,7 @@
// retroSoC is licensed under Mulan PSL v2.
module rib_adapter_formal;
localparam logic [2:0] RIB_RESP_SLVERR = 3'd3;
(* anyseq *) (* gclk *)reg clk_i;
wire rst_n_i;
wire f_past_valid;
@@ -11,20 +12,20 @@ module rib_adapter_formal;
wire w_valid, w_ready, wlast;
wire [31:0] wdata;
wire [ 3:0] wstrb;
wire rsp_valid, rsp_ready, rsp_last;
wire rsp_valid, rsp_ready, rsp_last, rsp_error;
wire [31:0] rsp_rdata;
wire [ 2:0] rsp_code;
wire [ 1:0] rsp_beat;
wire ribp_valid, ribp_ready;
wire ribp_valid, ribp_ready, ribp_resp_err;
wire [31:0] ribp_addr, ribp_wdata;
wire [3:0] ribp_wstrb;
wire source_valid, source_ready;
wire source_valid, source_ready, source_resp_err;
wire [31:0] source_addr;
wire [ 3:0] source_wstrb;
wire adapted_cmd_valid, adapted_cmd_ready;
wire [31:0] adapted_cmd_addr;
wire [ 1:0] adapted_cmd_len;
wire adapted_w_valid, adapted_w_ready, adapted_wlast;
wire adapted_w_valid, adapted_w_ready, adapted_wlast, adapted_rsp_error;
wire [31:0] adapted_wdata;
wire [ 3:0] adapted_wstrb;
@@ -62,6 +63,12 @@ module rib_adapter_formal;
assert (rsp_beat == $past(rsp_beat));
assert (rsp_last == $past(rsp_last));
end
if (f_past_valid && $past(rst_n_i && ribp_valid && ribp_ready && ribp_resp_err)) begin
assert (rsp_valid);
assert (rsp_error);
assert (rsp_code == RIB_RESP_SLVERR);
end
if (source_ready) assert (source_resp_err == adapted_rsp_error);
assert (rsp_beat <= 2'd3);
if (adapted_cmd_valid) assert (adapted_cmd_len == 2'd0);
if (adapted_w_valid) assert (adapted_wlast);
rtl/mini/formal/ribp2apb_formal.sv
+4
View File
@@ -31,9 +31,11 @@ module ribp2apb_formal_design (
output logic [31:0] rib_wdata,
output logic [ 3:0] rib_wstrb,
output logic rib_ready,
output logic rib_resp_err,
output logic [ 9:0] psel_comb,
output logic [ 9:0] psel_q,
output logic xfer_ready,
output logic xfer_error,
output logic [ 1:0] fsm_q
);
@@ -63,6 +65,7 @@ module ribp2apb_formal_design (
assign rib_wdata = rib.wdata;
assign rib_wstrb = rib.wstrb;
assign rib_ready = rib.ready;
assign rib_resp_err = rib.resp_err;
formal_apb_slave u_archinfo_slave (.apb(archinfo));
formal_apb_slave u_rng_slave (.apb(rng));
@@ -94,6 +97,7 @@ module ribp2apb_formal_design (
assign psel_comb = u_dut.s_psel_comb;
assign psel_q = u_dut.s_psel_q;
assign xfer_ready = u_dut.s_xfer_ready;
assign xfer_error = u_dut.s_xfer_error;
assign fsm_q = u_dut.s_fsm_q;
initial begin
rtl/mini/formal/ribp2apb_formal_props.sv
+7 -2
View File
@@ -20,10 +20,10 @@ module ribp2apb_formal;
wire [31:0] rib_addr;
wire [31:0] rib_wdata;
wire [ 3:0] rib_wstrb;
wire rib_ready;
wire rib_ready, rib_resp_err;
wire [9:0] psel_comb;
wire [9:0] psel_q;
wire xfer_ready;
wire xfer_ready, xfer_error;
wire [1:0] fsm_q;
ribp2apb_formal_design u_design (
@@ -35,9 +35,11 @@ module ribp2apb_formal;
.rib_wdata (rib_wdata),
.rib_wstrb (rib_wstrb),
.rib_ready (rib_ready),
.rib_resp_err(rib_resp_err),
.psel_comb (psel_comb),
.psel_q (psel_q),
.xfer_ready (xfer_ready),
.xfer_error (xfer_error),
.fsm_q (fsm_q)
);
@@ -55,6 +57,9 @@ module ribp2apb_formal;
if (rib_ready) begin
assert (xfer_ready);
assert (fsm_q == FSM_ENAB);
assert (rib_resp_err == xfer_error);
end else begin
assert (!rib_resp_err);
end
if (f_past_valid && $past(rst_n_i && fsm_q == FSM_SETP)) begin
assert (psel_q == $past(psel_q));
rtl/mini/formal/sysctrl_formal.sv
+1 -1
View File
@@ -61,7 +61,7 @@ module sysctrl_formal_design (
assign sysctrl.user_bus_idle_i = 1'b1;
assign sysctrl.fault_access_i = 1'b0;
assign sysctrl.fault_master_i = '0;
assign sysctrl.fault_code_i = f_fault_reserved ? `SOC_RIB_RESP_RESERVED : `SOC_RIB_RESP_DECERR;
assign sysctrl.fault_code_i = f_fault_reserved ? `RIB_RESP_RESERVED : `RIB_RESP_DECERR;
assign sysctrl.perf_mgmt_wait_i = '0;
assign sysctrl.perf_user_wait_i = '0;
assign sysctrl.perf_dma_wait_i = '0;
rtl/mini/integration/generate_soc_topology.py
+14 -9
View File
@@ -18,7 +18,7 @@ SV_REFERENCE_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*(?:\.[A-Za-z_][A-Za-z0-9_]*
SV_CONSTANT_RE = re.compile(r"(?:1'[bB][01]|'[01])$")
FABRIC_LINK_NAMES = ("mgmt", "user", "dma", "rib", "apb")
FABRIC_PROTOCOLS = {
"mgmt": "ribl",
"mgmt": "ribp",
"user": "rib",
"dma": "rib",
"rib": "rib",
@@ -550,6 +550,7 @@ def render_ribp_routes(
[
f" logic [{count - 1}:0] s_slv_sel_d, s_slv_sel_q;",
f" logic [{count - 1}:0] s_slv_ready;",
f" logic [{count - 1}:0] s_slv_resp_err;",
f" logic [31:0] s_slv_rdata [0:{count - 1}];",
"",
]
@@ -577,6 +578,7 @@ def render_ribp_routes(
f" assign {target.interface}.wstrb = ribp.wstrb;",
f" assign s_slv_sel_d[{target.slot}] = {target.interface}.valid;",
f" assign s_slv_ready[{target.slot}] = {target.interface}.ready;",
f" assign s_slv_resp_err[{target.slot}] = {target.interface}.resp_err;",
f" assign s_slv_rdata[{target.slot}] = {target.interface}.rdata;",
"",
]
@@ -591,6 +593,7 @@ def render_ribp_routes(
" );",
"",
" assign ribp.ready = |(s_slv_sel_q & s_slv_ready);",
" assign ribp.resp_err = |(s_slv_sel_q & s_slv_ready & s_slv_resp_err);",
"",
" always_comb begin",
" ribp.rdata = '0;",
@@ -706,9 +709,8 @@ def render_apb_response_mux(targets: list[ApbTarget]) -> str:
def render_fabric_interfaces(links: list[FabricLink]) -> str:
lines = ["// Generated by rtl/mini/integration/generate_soc_topology.py; do not edit."]
interface_types = {
"ribl": "soc_ribl_if",
"rib": "soc_rib_if",
"ribp": "ribp_if",
"rib": "rib_if",
}
lines.extend(
f" {interface_types[link.protocol]} {link.interface} ();"
@@ -730,7 +732,7 @@ def render_fabric_connection(links: list[FabricLink], name: str, port: str) -> s
def render_bus_fabric_connections(links: list[FabricLink]) -> str:
port_names = {
"mgmt": "mgmt_ribl",
"mgmt": "mgmt_ribp",
"user": "user_rib",
"dma": "dma_rib",
"rib": "rib",
@@ -876,8 +878,8 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
) = read_topology(topology_path, memory_map_path)
memory_regions = read_memory_regions(memory_map_path)
rtl_dir = output_dir / "rtl"
atomic_write(rtl_dir / "soc_ribp_interfaces.svh", render_ribp_interfaces(targets))
atomic_write(rtl_dir / "soc_ribp_routes.svh", render_ribp_routes(targets, memory_regions))
atomic_write(rtl_dir / "ribp_interfaces.svh", render_ribp_interfaces(targets))
atomic_write(rtl_dir / "ribp_routes.svh", render_ribp_routes(targets, memory_regions))
atomic_write(rtl_dir / "soc_apb_interfaces.svh", render_apb_interfaces(apb_targets))
atomic_write(rtl_dir / "soc_apb_bridges.svh", render_apb_bridges(apb_targets))
atomic_write(rtl_dir / "soc_apb_ports.svh", render_apb_ports(apb_targets))
@@ -889,7 +891,7 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
atomic_write(rtl_dir / "soc_fabric_interfaces.svh", render_fabric_interfaces(fabric_links))
atomic_write(
rtl_dir / "soc_mgmt_core_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "mgmt", "ribl"),
render_fabric_connection(fabric_links, "mgmt", "ribp"),
)
atomic_write(
rtl_dir / "soc_user_core_fabric.svh",
@@ -897,7 +899,7 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
)
atomic_write(rtl_dir / "soc_bus_fabric.svh", render_bus_fabric_connections(fabric_links))
atomic_write(
rtl_dir / "soc_ip_ribp_wrapper_fabric.svh",
rtl_dir / "ip_ribp_wrapper_fabric.svh",
render_fabric_connection(fabric_links, "rib", "rib")
+ render_fabric_connection(fabric_links, "dma", "dma_rib"),
)
@@ -908,8 +910,11 @@ def generate(topology_path: Path, memory_map_path: Path, output_dir: Path) -> No
atomic_write(rtl_dir / "soc_gpio_alt_bindings.svh", render_gpio_bindings(gpio_functions))
atomic_write(rtl_dir / "soc_irq_config.svh", render_irq_config(irq_vector_width, irq_groups))
for group in irq_groups:
filename = f"{group.name}_irq_bindings.svh"
if group.name != "ribp":
filename = f"soc_{group.name}_irq_bindings.svh"
atomic_write(
rtl_dir / f"soc_{group.name}_irq_bindings.svh",
rtl_dir / filename,
render_irq_group_bindings(group, interrupts),
)
atomic_write(
rtl/mini/integration/generate_user_extensions.py
+1 -1
View File
@@ -130,7 +130,7 @@ def render_core_bindings(extensions: ExtensionMap) -> str:
for target in extensions.core_targets:
lines.extend(
[
f" soc_rib_if u_user_{target.slot}_rib_if ();",
f" rib_if u_user_{target.slot}_rib_if ();",
f" logic [31:0] s_user_{target.slot}_irq;",
]
)
rtl/mini/integration/soc_topology.json
+1 -1
View File
@@ -46,7 +46,7 @@
{"slot": 17, "name": "i2c1", "interface": "u_i2c1_ribp_if", "regions": ["RIBP_I2C1"]}
],
"fabric_links": [
{"name": "mgmt", "interface": "u_mgmt_ribl_if", "protocol": "ribl"},
{"name": "mgmt", "interface": "u_mgmt_ribp_if", "protocol": "ribp"},
{"name": "user", "interface": "u_user_rib_if", "protocol": "rib"},
{"name": "dma", "interface": "u_dma_rib_if", "protocol": "rib"},
{"name": "rib", "interface": "u_rib_if", "protocol": "rib"},
rtl/mini/mk/formal.mk
+5 -6
View File
@@ -23,12 +23,11 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal.sv \
$(RTL_PATH)/formal/gpio_user_formal_props.sv \
$(RTL_PATH)/top/bus.sv \
$(RTL_PATH)/top/soc_rib_error_slave.sv \
$(RTL_PATH)/top/soc_ribl_if.sv \
$(RTL_PATH)/top/soc_rib_if.sv \
$(RTL_PATH)/top/soc_rib2ram.sv \
$(RTL_PATH)/top/soc_rib2ribp.sv \
$(RTL_PATH)/top/soc_ribl2rib.sv \
$(RTL_PATH)/top/rib_error_slave.sv \
$(RTL_PATH)/top/rib_if.sv \
$(RTL_PATH)/top/rib2ram.sv \
$(RTL_PATH)/top/rib2ribp.sv \
$(RTL_PATH)/top/ribp2rib.sv \
$(ROOT_PATH)/rtl/ip/ribp/interconnect/ribp2apb.sv \
$(ROOT_PATH)/rtl/ip/ribp/interconnect/ribp_regslice.sv \
$(ROOT_PATH)/rtl/ip/ribp/peripheral/gpio.sv \
rtl/mini/top/ahbl2soc_ribl.sv → rtl/mini/top/ahbl2ribp.sv
+27 -28
View File
@@ -8,13 +8,12 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
// Management-core AHB-Lite to SoC RIB bridge. It is intentionally separate
// from the managed-compatible ahbl2ribp used by externally supplied user cores.
module ahbl2soc_ribl (
// Management-core AHB-Lite to scalar RIBP bridge.
module ahbl2ribp (
ahbl_if.slave ahbl,
soc_ribl_if.master ribl
ribp_if.master ribp
);
localparam logic [1:0] AHBL_TRANS_NSEQ = 2'b10;
@@ -31,49 +30,49 @@ module ahbl2soc_ribl (
logic s_hwrite_d, s_hwrite_q;
logic [2:0] s_hsize_d, s_hsize_q;
assign ahbl.hready = s_fsm_q == STATE_IDLE || ribl.ready;
assign ahbl.hresp = ribl.ready && ribl.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = ribl.rdata;
assign ribl.valid = s_fsm_q != STATE_IDLE;
assign ribl.addr = {s_haddr_q[31:2], 2'b00};
assign ahbl.hready = s_fsm_q == STATE_IDLE || ribp.ready;
assign ahbl.hresp = ribp.ready && ribp.resp_err ? AHBL_RESP_ERROR : AHBL_RESP_OKAY;
assign ahbl.hrdata = ribp.rdata;
assign ribp.valid = s_fsm_q != STATE_IDLE;
assign ribp.addr = {s_haddr_q[31:2], 2'b00};
always_comb begin
ribl.wstrb = '0;
ribl.wdata = '0;
ribp.wstrb = '0;
ribp.wdata = '0;
if (s_hwrite_q) begin
unique case (s_hsize_q)
AHBL_SIZE_BYTE: begin
unique case (s_haddr_q[1:0])
2'd0: begin
ribl.wstrb = 4'b0001;
ribl.wdata = {24'd0, ahbl.hwdata[7:0]};
ribp.wstrb = 4'b0001;
ribp.wdata = {24'd0, ahbl.hwdata[7:0]};
end
2'd1: begin
ribl.wstrb = 4'b0010;
ribl.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
ribp.wstrb = 4'b0010;
ribp.wdata = {16'd0, ahbl.hwdata[7:0], 8'd0};
end
2'd2: begin
ribl.wstrb = 4'b0100;
ribl.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
ribp.wstrb = 4'b0100;
ribp.wdata = {8'd0, ahbl.hwdata[7:0], 16'd0};
end
default: begin
ribl.wstrb = 4'b1000;
ribl.wdata = {ahbl.hwdata[7:0], 24'd0};
ribp.wstrb = 4'b1000;
ribp.wdata = {ahbl.hwdata[7:0], 24'd0};
end
endcase
end
AHBL_SIZE_HWRD: begin
if (s_haddr_q[1]) begin
ribl.wstrb = 4'b1100;
ribl.wdata = {ahbl.hwdata[15:0], 16'd0};
ribp.wstrb = 4'b1100;
ribp.wdata = {ahbl.hwdata[15:0], 16'd0};
end else begin
ribl.wstrb = 4'b0011;
ribl.wdata = {16'd0, ahbl.hwdata[15:0]};
ribp.wstrb = 4'b0011;
ribp.wdata = {16'd0, ahbl.hwdata[15:0]};
end
end
default: begin
ribl.wstrb = 4'b1111;
ribl.wdata = ahbl.hwdata;
ribp.wstrb = 4'b1111;
ribp.wdata = ahbl.hwdata;
end
endcase
end
@@ -94,7 +93,7 @@ module ahbl2soc_ribl (
end
end
STATE_DATA: begin
if (!ribl.ready) begin
if (!ribp.ready) begin
s_fsm_d = STATE_WAIT;
end else if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_haddr_d = ahbl.haddr;
@@ -105,7 +104,7 @@ module ahbl2soc_ribl (
end
end
STATE_WAIT: begin
if (ribl.ready) begin
if (ribp.ready) begin
if (ahbl.htrans == AHBL_TRANS_NSEQ) begin
s_fsm_d = STATE_DATA;
s_haddr_d = ahbl.haddr;
rtl/mini/top/bus.sv
+30 -33
View File
@@ -9,7 +9,7 @@
// See the Mulan PSL v2 for more details.
`include "mmap_define.svh"
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
module bus (
// verilog_format: off
@@ -18,14 +18,13 @@ module bus (
`ifdef HAVE_SRAM_IF
ram_if.master ram,
`endif
soc_ribl_if.slave mgmt_ribl,
soc_rib_if.slave user_rib,
soc_rib_if.slave dma_rib,
ribp_if.slave mgmt_ribp,
rib_if.slave user_rib,
rib_if.slave dma_rib,
input logic user_bus_enable_i,
output logic user_bus_idle_o,
soc_rib_if.master rib,
rib_if.master rib,
ribp_if.master apb_ribp,
input logic apb_resp_err_i,
input logic perf_enable_i,
input logic perf_clear_i,
output logic fault_valid_o,
@@ -55,11 +54,11 @@ module bus (
localparam logic [1:0] TARGET_RAM = 2'd2;
localparam logic [1:0] TARGET_FAULT = 2'd3;
soc_rib_if u_mgmt_rib_if ();
soc_rib_if u_mstr_rib_if ();
soc_rib_if u_apb_rib_if ();
soc_rib_if u_ram_rib_if ();
soc_rib_if u_fault_rib_if ();
rib_if u_mgmt_rib_if ();
rib_if u_mstr_rib_if ();
rib_if u_apb_rib_if ();
rib_if u_ram_rib_if ();
rib_if u_fault_rib_if ();
logic s_mstr_lock_d, s_mstr_lock_q;
logic s_cmd_accepted_d, s_cmd_accepted_q;
@@ -91,23 +90,21 @@ module bus (
logic [63:0] s_perf_psram_wait_d, s_perf_psram_wait_q;
logic [63:0] s_perf_flash_wait_d, s_perf_flash_wait_q;
soc_ribl2rib u_mgmt_ribl2rib (
ribp2rib u_mgmt_ribp2rib (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribl (mgmt_ribl),
.ribp (mgmt_ribp),
.rib (u_mgmt_rib_if)
);
soc_rib2ribp u_apb_rib2ribp (
rib2ribp u_apb_rib2ribp (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribp_resp_err_i (apb_resp_err_i),
.ribp_resp_code_i(`SOC_RIB_RESP_SLVERR),
.rib (u_apb_rib_if),
.ribp (apb_ribp)
);
soc_rib_error_slave u_fault_slave (
rib_error_slave u_fault_slave (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.error_code_i(s_fault_code),
@@ -115,7 +112,7 @@ module bus (
);
`ifdef HAVE_SRAM_IF
soc_rib2ram u_rib2ram (
rib2ram u_rib2ram (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (u_ram_rib_if),
@@ -127,7 +124,7 @@ module bus (
assign u_ram_rib_if.rsp_valid = 1'b0;
assign u_ram_rib_if.rdata = '0;
assign u_ram_rib_if.resp_err = 1'b0;
assign u_ram_rib_if.resp_code = `SOC_RIB_RESP_OK;
assign u_ram_rib_if.resp_code = `RIB_RESP_OK;
assign u_ram_rib_if.rsp_beat = '0;
assign u_ram_rib_if.rsp_last = 1'b0;
`endif
@@ -230,7 +227,7 @@ module bus (
u_mstr_rib_if.cmd_valid = 1'b0;
u_mstr_rib_if.cmd_addr = '0;
u_mstr_rib_if.cmd_write = 1'b0;
u_mstr_rib_if.cmd_len = `SOC_RIB_LEN_INCR1;
u_mstr_rib_if.cmd_len = `RIB_LEN_INCR1;
u_mstr_rib_if.w_valid = 1'b0;
u_mstr_rib_if.wdata = '0;
u_mstr_rib_if.wstrb = '0;
@@ -314,13 +311,13 @@ module bus (
// verilog_format: off
assign s_last_addr = u_mstr_rib_if.cmd_addr +
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR4 ? 32'd12 : 32'd0);
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4 ? 32'd12 : 32'd0);
assign s_length_legal =
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) ||
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR4);
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) ||
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4);
assign s_burst_legal =
s_length_legal &&
((u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) ||
((u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) ||
((u_mstr_rib_if.cmd_addr[3:0] == 4'b0000) &&
`SOC_ADDR_SUPPORTS_INCR4(u_mstr_rib_if.cmd_addr) &&
`SOC_ADDR_SUPPORTS_INCR4(s_last_addr)));
@@ -336,7 +333,7 @@ module bus (
assign s_ribp_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
s_burst_legal && `SOC_ADDR_IS_RIBP(u_mstr_rib_if.cmd_addr);
assign s_apb_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
(u_mstr_rib_if.cmd_len == `SOC_RIB_LEN_INCR1) &&
(u_mstr_rib_if.cmd_len == `RIB_LEN_INCR1) &&
`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr);
`ifdef HAVE_SRAM_IF
assign s_ram_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied &&
@@ -349,20 +346,20 @@ module bus (
// verilog_format: on
always_comb begin
s_fault_code = `SOC_RIB_RESP_DECERR;
s_fault_code = `RIB_RESP_DECERR;
if (s_access_denied) begin
s_fault_code = `SOC_RIB_RESP_PROTERR;
s_fault_code = `RIB_RESP_PROTERR;
end else if (`SOC_ADDR_IS_RESERVED(u_mstr_rib_if.cmd_addr)) begin
s_fault_code = `SOC_RIB_RESP_RESERVED;
s_fault_code = `RIB_RESP_RESERVED;
// verilog_format: off
end else if ((`SOC_ADDR_IS_RIBP(u_mstr_rib_if.cmd_addr) ||
`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) ||
`SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr)) &&
(~s_burst_legal ||
(`SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) &&
(u_mstr_rib_if.cmd_len != `SOC_RIB_LEN_INCR1)))) begin
(u_mstr_rib_if.cmd_len != `RIB_LEN_INCR1)))) begin
// verilog_format: on
s_fault_code = `SOC_RIB_RESP_BURSTERR;
s_fault_code = `RIB_RESP_BURSTERR;
end
end
@@ -462,7 +459,7 @@ module bus (
u_mstr_rib_if.rsp_valid = 1'b0;
u_mstr_rib_if.rdata = '0;
u_mstr_rib_if.resp_err = 1'b0;
u_mstr_rib_if.resp_code = `SOC_RIB_RESP_OK;
u_mstr_rib_if.resp_code = `RIB_RESP_OK;
u_mstr_rib_if.rsp_beat = '0;
u_mstr_rib_if.rsp_last = 1'b0;
unique case (s_target_q)
@@ -555,8 +552,8 @@ module bus (
u_fault_rib_if.rsp_valid && u_fault_rib_if.rsp_ready;
assign fault_addr_o = s_fault_addr_q;
assign fault_wstrb_o = s_fault_wstrb_q;
assign fault_reserved_o = s_fault_code_q == `SOC_RIB_RESP_RESERVED;
assign fault_access_o = s_fault_code_q == `SOC_RIB_RESP_PROTERR;
assign fault_reserved_o = s_fault_code_q == `RIB_RESP_RESERVED;
assign fault_access_o = s_fault_code_q == `RIB_RESP_PROTERR;
assign fault_master_o = s_fault_master_q;
assign fault_code_o = s_fault_code_q;
rtl/mini/top/core_wrapper.sv
+2 -2
View File
@@ -13,7 +13,7 @@ module core_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [31:0] irq_i,
soc_ribl_if.master ribl
ribp_if.master ribp
// verilog_format: on
);
@@ -21,7 +21,7 @@ module core_wrapper (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.irq_i (irq_i),
.ribl (ribl)
.ribp (ribp)
);
endmodule
rtl/mini/top/ip_apb_wrapper.sv
-2
View File
@@ -28,7 +28,6 @@ module ip_apb_wrapper (
ps2_if.dut ps2,
input logic [`USER_IPSEL_WIDTH-1:0] ip_sel_i,
user_gpio_if.user_ip user_gpio,
output logic ribp_resp_err_o,
output logic [`SOC_IRQ_APB_WIDTH-1:0] irq_o
// verilog_format: on
);
@@ -67,7 +66,6 @@ ribp2apb u_ribp2apb (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribp (ribp),
.resp_err_o(ribp_resp_err_o),
`include "soc_apb_connections.svh"
);
rtl/mini/top/ip_ribp_wrapper.sv
+7 -9
View File
@@ -10,7 +10,7 @@
`include "mmap_define.svh"
`include "soc_irq_config.svh"
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
module ip_ribp_wrapper (
// verilog_format: off
@@ -18,7 +18,7 @@ module ip_ribp_wrapper (
input logic rst_n_i,
input logic clk_aud_i,
input logic rst_aud_n_i,
soc_rib_if.slave rib,
rib_if.slave rib,
gpio_if.dut gpio,
user_gpio_if.padctrl user_gpio,
uart_if.dut uart,
@@ -28,7 +28,7 @@ module ip_ribp_wrapper (
i2s_if.dut i2s,
onewire_if.dut onewire,
xpi_if.dut xpi,
soc_rib_if.master dma_rib,
rib_if.master dma_rib,
sysctrl_if.dut sysctrl,
pll_ctrl_if.sysctrl pll_ctrl,
sdram_if.dut sdram,
@@ -46,7 +46,7 @@ module ip_ribp_wrapper (
// verilog_format: off
// Generated RIBP target declarations preserve scalar-interface compatibility.
`include "soc_ribp_interfaces.svh"
`include "ribp_interfaces.svh"
ribp_if ribp ();
// verilog_format: on
@@ -59,11 +59,9 @@ module ip_ribp_wrapper (
logic s_dma_xfer_done;
logic s_tim0_irq, s_tim1_irq;
soc_rib2ribp u_rib2ribp (
rib2ribp u_rib2ribp (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribp_resp_err_i (1'b0),
.ribp_resp_code_i(`SOC_RIB_RESP_OK),
.rib (rib),
.ribp (ribp)
);
@@ -77,11 +75,11 @@ module ip_ribp_wrapper (
assign u_dma_hw_trg_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
// Uses ClusterIP common ribp_if and register.sv dffr through generated bindings.
`include "soc_ribp_routes.svh"
`include "ribp_routes.svh"
// verilog_format: off
// Generated IRQ ownership and core-vector bit assignments are topology checked.
`include "soc_ribp_irq_bindings.svh"
`include "ribp_irq_bindings.svh"
ribp_gpio u_rib_gpio (
.clk_i (clk_i),
rtl/mini/top/mgmt_core_wrapper.sv
+8 -8
View File
@@ -15,7 +15,7 @@ module mgmt_core_wrapper (
input logic clk_i,
input logic rst_n_i,
input logic [31:0] irq_i,
soc_ribl_if.master ribl
ribp_if.master ribp
// verilog_format: on
);
@@ -33,13 +33,13 @@ module mgmt_core_wrapper (
.clk (clk_i),
.resetn (rst_n_i),
.trap (),
.mem_valid (ribl.valid),
.mem_valid (ribp.valid),
.mem_instr (),
.mem_addr (ribl.addr),
.mem_wdata (ribl.wdata),
.mem_wstrb (ribl.wstrb),
.mem_rdata (ribl.rdata),
.mem_ready (ribl.ready),
.mem_addr (ribp.addr),
.mem_wdata (ribp.wdata),
.mem_wstrb (ribp.wstrb),
.mem_rdata (ribp.rdata),
.mem_ready (ribp.ready),
.mem_la_read (),
.mem_la_write(),
.mem_la_addr (),
@@ -62,7 +62,7 @@ module mgmt_core_wrapper (
logic s_pwrup_req;
// verilog_format: off
ahbl_if u_ahbl_if (clk_i, rst_n_i);
ahbl2soc_ribl u_ahbl2soc_ribl (u_ahbl_if, ribl);
ahbl2ribp u_ahbl2ribp (u_ahbl_if, ribp);
// verilog_format: on
hazard3_cpu_1port #(
rtl/mini/top/retrosoc.sv
+1 -4
View File
@@ -62,7 +62,6 @@ module retrosoc (
logic s_bus_fault_access;
logic [ 1:0] s_bus_fault_master;
logic [ 2:0] s_bus_fault_code;
logic s_apb_resp_err;
logic s_perf_enable;
logic s_perf_clear;
logic [ 63:0] s_perf_mgmt_wait;
@@ -126,7 +125,6 @@ core_wrapper u_core_wrapper (
.user_bus_enable_i(u_sysctrl_if.user_bus_enable_o),
.user_bus_idle_o (u_sysctrl_if.user_bus_idle_i),
`include "soc_bus_fabric.svh"
.apb_resp_err_i (s_apb_resp_err),
.perf_enable_i (s_perf_enable),
.perf_clear_i (s_perf_clear),
.fault_valid_o (s_bus_fault_valid),
@@ -151,7 +149,7 @@ core_wrapper u_core_wrapper (
.rst_n_i (rst_n_i),
.clk_aud_i (clk_aud_i),
.rst_aud_n_i (rst_aud_n_i),
`include "soc_ip_ribp_wrapper_fabric.svh"
`include "ip_ribp_wrapper_fabric.svh"
.gpio (u_gpio_if),
.user_gpio (u_user_gpio_if),
.uart (uart0),
@@ -187,7 +185,6 @@ core_wrapper u_core_wrapper (
.ps2 (u_ps2_if),
.ip_sel_i (u_sysctrl_if.ip_sel_o),
.user_gpio (u_user_gpio_if),
.ribp_resp_err_o(s_apb_resp_err),
.irq_o (s_apb_irq)
);
rtl/mini/top/soc_rib2ram.sv → rtl/mini/top/rib2ram.sv
+5 -5
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
module soc_rib2ram (
module rib2ram (
input logic clk_i,
input logic rst_n_i,
soc_rib_if.slave rib,
rib_if.slave rib,
ram_if.master ram
);
@@ -66,9 +66,9 @@ module soc_rib2ram (
assign s_rsp_input_valid = s_write_q ? s_write_rsp_valid : s_read_pending_q;
assign s_rsp_input_data = s_write_q ?
{1'b1, s_write_beat_q,
s_write_rsp_error ? `SOC_RIB_RESP_BURSTERR : `SOC_RIB_RESP_OK,
s_write_rsp_error ? `RIB_RESP_BURSTERR : `RIB_RESP_OK,
s_write_rsp_error, 32'd0} :
{s_read_last_q, s_read_beat_q, `SOC_RIB_RESP_OK, 1'b0, ram.rdata};
{s_read_last_q, s_read_beat_q, `RIB_RESP_OK, 1'b0, ram.rdata};
spill_register #(
.DATA_WIDTH(RSP_WIDTH),
rtl/mini/top/soc_rib2ribp.sv → rtl/mini/top/rib2ribp.sv
+10 -12
View File
@@ -8,14 +8,12 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_rib_defs.svh"
`include "rib_defs.svh"
module soc_rib2ribp (
module rib2ribp (
input logic clk_i,
input logic rst_n_i,
input logic ribp_resp_err_i,
input logic [2:0] ribp_resp_code_i,
soc_rib_if.slave rib,
rib_if.slave rib,
ribp_if.master ribp
);
@@ -38,8 +36,8 @@ module soc_rib2ribp (
logic s_cmd_legal;
logic s_cmd_hdshk, s_w_hdshk, s_ribp_hdshk, s_rsp_hdshk;
assign s_cmd_legal = (rib.cmd_len == `SOC_RIB_LEN_INCR1) ||
((rib.cmd_len == `SOC_RIB_LEN_INCR4) &&
assign s_cmd_legal = (rib.cmd_len == `RIB_LEN_INCR1) ||
((rib.cmd_len == `RIB_LEN_INCR4) &&
(rib.cmd_addr[3:0] == 4'b0000));
assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready;
assign s_w_hdshk = rib.w_valid && rib.w_ready;
@@ -51,7 +49,7 @@ module soc_rib2ribp (
assign rib.rsp_valid = s_fsm_q == FSM_RESP;
assign rib.rdata = s_rdata_q;
assign rib.resp_err = s_error_q;
assign rib.resp_code = s_error_q ? s_error_code_q : `SOC_RIB_RESP_OK;
assign rib.resp_code = s_error_q ? s_error_code_q : `RIB_RESP_OK;
assign rib.rsp_beat = s_beat_q;
assign rib.rsp_last = s_write_q || (s_beat_q == s_len_q) || s_error_q;
@@ -76,7 +74,7 @@ module soc_rib2ribp (
s_beat_d = '0;
s_write_d = rib.cmd_write;
s_error_d = ~s_cmd_legal;
s_error_code_d = s_cmd_legal ? `SOC_RIB_RESP_OK : `SOC_RIB_RESP_BURSTERR;
s_error_code_d = s_cmd_legal ? `RIB_RESP_OK : `RIB_RESP_BURSTERR;
if (~s_cmd_legal) begin
s_fsm_d = rib.cmd_write ? FSM_DROP_WDATA : FSM_RESP;
end else begin
@@ -88,7 +86,7 @@ module soc_rib2ribp (
if (s_w_hdshk) begin
if (rib.wlast != (s_beat_q == s_len_q)) begin
s_error_d = 1'b1;
s_error_code_d = `SOC_RIB_RESP_BURSTERR;
s_error_code_d = `RIB_RESP_BURSTERR;
s_fsm_d = FSM_RESP;
end else begin
s_fsm_d = FSM_RIBP;
@@ -97,9 +95,9 @@ module soc_rib2ribp (
end
FSM_RIBP: begin
if (s_ribp_hdshk) begin
if (ribp_resp_err_i) begin
if (ribp.resp_err) begin
s_error_d = 1'b1;
s_error_code_d = ribp_resp_code_i;
s_error_code_d = `RIB_RESP_SLVERR;
s_fsm_d = FSM_RESP;
end else if (s_write_q) begin
if (s_beat_q == s_len_q) begin
rtl/mini/top/soc_rib_defs.svh → rtl/mini/top/rib_defs.svh
+11 -11
View File
@@ -8,18 +8,18 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RETROSOC_SOC_RIB_DEFS_SVH
`define RETROSOC_SOC_RIB_DEFS_SVH
`ifndef RETROSOC_RIB_DEFS_SVH
`define RETROSOC_RIB_DEFS_SVH
`define SOC_RIB_RESP_OK 3'd0
`define SOC_RIB_RESP_DECERR 3'd1
`define SOC_RIB_RESP_PROTERR 3'd2
`define SOC_RIB_RESP_SLVERR 3'd3
`define SOC_RIB_RESP_TIMEOUT 3'd4
`define SOC_RIB_RESP_RESERVED 3'd5
`define SOC_RIB_RESP_BURSTERR 3'd6
`define RIB_RESP_OK 3'd0
`define RIB_RESP_DECERR 3'd1
`define RIB_RESP_PROTERR 3'd2
`define RIB_RESP_SLVERR 3'd3
`define RIB_RESP_TIMEOUT 3'd4
`define RIB_RESP_RESERVED 3'd5
`define RIB_RESP_BURSTERR 3'd6
`define SOC_RIB_LEN_INCR1 2'd0
`define SOC_RIB_LEN_INCR4 2'd3
`define RIB_LEN_INCR1 2'd0
`define RIB_LEN_INCR4 2'd3
`endif
rtl/mini/top/soc_rib_error_slave.sv → rtl/mini/top/rib_error_slave.sv
+2 -2
View File
@@ -8,11 +8,11 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
module soc_rib_error_slave (
module rib_error_slave (
input logic clk_i,
input logic rst_n_i,
input logic [2:0] error_code_i,
soc_rib_if.slave rib
rib_if.slave rib
);
localparam logic [1:0] FSM_CMD = 2'd0;
rtl/mini/top/soc_rib_if.sv → rtl/mini/top/rib_if.sv
+3 -3
View File
@@ -8,12 +8,12 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RETROSOC_SOC_RIB_IF_SV
`define RETROSOC_SOC_RIB_IF_SV
`ifndef RETROSOC_RIB_IF_SV
`define RETROSOC_RIB_IF_SV
// SoC-owned split-channel RIB contract. Version 1 supports one outstanding
// 32-bit INCR1 or INCR4 transaction and does not carry transaction IDs.
interface soc_rib_if ();
interface rib_if ();
logic cmd_valid;
logic cmd_ready;
rtl/mini/top/ribp2rib.sv
+90 -16
View File
@@ -8,32 +8,106 @@
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
// Compatibility adapter for ClusterIP's status-less RIBP interface.
`include "rib_defs.svh"
module ribp2rib #(
parameter bit SYNC_RESET = 1'b0
) (
input logic clk_i,
input logic rst_n_i,
ribp_if.slave ribp,
soc_rib_if.master rib
rib_if.master rib
);
soc_ribl_if u_soc_ribl_if ();
localparam logic [1:0] FSM_CMD = 2'd0;
localparam logic [1:0] FSM_WDATA = 2'd1;
localparam logic [1:0] FSM_RESP = 2'd2;
assign u_soc_ribl_if.valid = ribp.valid;
assign u_soc_ribl_if.addr = ribp.addr;
assign u_soc_ribl_if.wdata = ribp.wdata;
assign u_soc_ribl_if.wstrb = ribp.wstrb;
assign ribp.ready = u_soc_ribl_if.ready;
assign ribp.rdata = u_soc_ribl_if.rdata;
logic [1:0] s_fsm_d, s_fsm_q;
logic [31:0] s_wdata_q;
logic [ 3:0] s_wstrb_q;
logic s_cmd_hdshk;
soc_ribl2rib #(
.SYNC_RESET(SYNC_RESET)
) u_soc_ribl2rib (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.ribl (u_soc_ribl_if),
.rib (rib)
assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready;
assign rib.cmd_valid = s_fsm_q == FSM_CMD && ribp.valid;
assign rib.cmd_addr = ribp.addr;
assign rib.cmd_write = |ribp.wstrb;
assign rib.cmd_len = `RIB_LEN_INCR1;
assign rib.w_valid = s_fsm_q == FSM_WDATA;
assign rib.wdata = s_wdata_q;
assign rib.wstrb = s_wstrb_q;
assign rib.wlast = 1'b1;
assign rib.rsp_ready = s_fsm_q == FSM_RESP;
assign ribp.ready = s_fsm_q == FSM_RESP && rib.rsp_valid;
assign ribp.rdata = rib.rdata;
assign ribp.resp_err = ribp.ready && rib.resp_err;
always_comb begin
s_fsm_d = s_fsm_q;
unique case (s_fsm_q)
FSM_CMD: begin
if (s_cmd_hdshk) begin
s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_RESP;
end
end
FSM_WDATA: begin
if (rib.w_valid && rib.w_ready) begin
s_fsm_d = FSM_RESP;
end
end
FSM_RESP: begin
if (rib.rsp_valid) begin
s_fsm_d = FSM_CMD;
end
end
default: s_fsm_d = FSM_CMD;
endcase
end
if (SYNC_RESET) begin : GEN_SYNC_RESET
dffsr #(2) u_fsm_dffsr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffesr #(32) u_wdata_dffesr (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribp.wdata,
s_wdata_q
);
dffesr #(4) u_wstrb_dffesr (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribp.wstrb,
s_wstrb_q
);
end else begin : GEN_ASYNC_RESET
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffer #(32) u_wdata_dffer (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribp.wdata,
s_wdata_q
);
dffer #(4) u_wstrb_dffer (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribp.wstrb,
s_wstrb_q
);
end
endmodule
rtl/mini/top/soc_ribl2rib.sv
-113
View File
@@ -1,113 +0,0 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_rib_defs.svh"
module soc_ribl2rib #(
parameter bit SYNC_RESET = 1'b0
) (
input logic clk_i,
input logic rst_n_i,
soc_ribl_if.slave ribl,
soc_rib_if.master rib
);
localparam logic [1:0] FSM_CMD = 2'd0;
localparam logic [1:0] FSM_WDATA = 2'd1;
localparam logic [1:0] FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic [31:0] s_wdata_q;
logic [ 3:0] s_wstrb_q;
logic s_cmd_hdshk;
assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready;
assign rib.cmd_valid = s_fsm_q == FSM_CMD && ribl.valid;
assign rib.cmd_addr = ribl.addr;
assign rib.cmd_write = |ribl.wstrb;
assign rib.cmd_len = `SOC_RIB_LEN_INCR1;
assign rib.w_valid = s_fsm_q == FSM_WDATA;
assign rib.wdata = s_wdata_q;
assign rib.wstrb = s_wstrb_q;
assign rib.wlast = 1'b1;
assign rib.rsp_ready = s_fsm_q == FSM_RESP;
assign ribl.ready = s_fsm_q == FSM_RESP && rib.rsp_valid;
assign ribl.rdata = rib.rdata;
assign ribl.resp_err = ribl.ready && rib.resp_err;
always_comb begin
s_fsm_d = s_fsm_q;
unique case (s_fsm_q)
FSM_CMD: begin
if (s_cmd_hdshk) begin
s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_RESP;
end
end
FSM_WDATA: begin
if (rib.w_valid && rib.w_ready) begin
s_fsm_d = FSM_RESP;
end
end
FSM_RESP: begin
if (rib.rsp_valid) begin
s_fsm_d = FSM_CMD;
end
end
default: s_fsm_d = FSM_CMD;
endcase
end
if (SYNC_RESET) begin : GEN_SYNC_RESET
dffsr #(2) u_fsm_dffsr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffesr #(32) u_wdata_dffesr (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribl.wdata,
s_wdata_q
);
dffesr #(4) u_wstrb_dffesr (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribl.wstrb,
s_wstrb_q
);
end else begin : GEN_ASYNC_RESET
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffer #(32) u_wdata_dffer (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribl.wdata,
s_wdata_q
);
dffer #(4) u_wstrb_dffer (
clk_i,
rst_n_i,
s_cmd_hdshk,
ribl.wstrb,
s_wstrb_q
);
end
endmodule
rtl/mini/top/soc_ribl_if.sv
-49
View File
@@ -1,49 +0,0 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`ifndef RETROSOC_SOC_RIBL_IF_SV
`define RETROSOC_SOC_RIBL_IF_SV
`include "soc_rib_defs.svh"
// SoC-owned RIBL fabric contract. RIBP IP remains on ClusterIP's ribp_if;
// this interface adds a response status only on the SoC master side.
interface soc_ribl_if ();
logic valid;
logic [31:0] addr;
logic [31:0] wdata;
logic [ 3:0] wstrb;
logic [31:0] rdata;
logic ready;
logic resp_err;
modport slave(
input valid,
input addr,
input wdata,
input wstrb,
output rdata,
output ready,
output resp_err
);
modport master(
output valid,
output addr,
output wdata,
output wstrb,
input rdata,
input ready,
input resp_err
);
endinterface
`endif
rtl/mini/top/soc_ribl_regslice.sv
-130
View File
@@ -1,130 +0,0 @@
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
// retroSoC is licensed under Mulan PSL v2.
// You can use this software according to the terms and conditions of the Mulan PSL v2.
// You may obtain a copy of Mulan PSL v2 at:
// http://license.coscl.org.cn/MulanPSL2
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// See the Mulan PSL v2 for more details.
`include "soc_rib_defs.svh"
module soc_ribl_regslice (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
soc_ribl_if.slave rib_slv,
soc_ribl_if.master rib_mst
// verilog_format: on
);
localparam logic [1:0] FSM_IDLE = 2'd0;
localparam logic [1:0] FSM_REQ = 2'd1;
localparam logic [1:0] FSM_RESP = 2'd2;
logic [1:0] s_fsm_d, s_fsm_q;
logic s_rib_mst_valid_d, s_rib_mst_valid_q;
logic [31:0] s_rib_mst_addr_d, s_rib_mst_addr_q;
logic [31:0] s_rib_mst_wdata_d, s_rib_mst_wdata_q;
logic [3:0] s_rib_mst_wstrb_d, s_rib_mst_wstrb_q;
logic [31:0] s_rib_mst_rdata_d, s_rib_mst_rdata_q;
logic s_rib_mst_ready_d, s_rib_mst_ready_q;
logic s_rib_mst_resp_err_d, s_rib_mst_resp_err_q;
assign rib_mst.valid = s_rib_mst_valid_q;
assign rib_mst.addr = s_rib_mst_addr_q;
assign rib_mst.wdata = s_rib_mst_wdata_q;
assign rib_mst.wstrb = s_rib_mst_wstrb_q;
always_comb begin
s_fsm_d = s_fsm_q;
s_rib_mst_valid_d = s_rib_mst_valid_q;
s_rib_mst_addr_d = s_rib_mst_addr_q;
s_rib_mst_wdata_d = s_rib_mst_wdata_q;
s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
s_rib_mst_ready_d = s_rib_mst_ready_q;
s_rib_mst_rdata_d = s_rib_mst_rdata_q;
s_rib_mst_resp_err_d = s_rib_mst_resp_err_q;
rib_slv.ready = 1'b0;
rib_slv.rdata = '0;
rib_slv.resp_err = 1'b0;
unique case (s_fsm_q)
FSM_IDLE: begin
if (rib_slv.valid) begin
s_fsm_d = FSM_REQ;
s_rib_mst_valid_d = 1'b1;
s_rib_mst_addr_d = rib_slv.addr;
s_rib_mst_wdata_d = rib_slv.wdata;
s_rib_mst_wstrb_d = rib_slv.wstrb;
end
end
FSM_REQ: begin
if (rib_mst.ready) begin
s_fsm_d = FSM_RESP;
s_rib_mst_valid_d = 1'b0;
s_rib_mst_ready_d = 1'b1;
s_rib_mst_rdata_d = rib_mst.rdata;
s_rib_mst_resp_err_d = rib_mst.resp_err;
end
end
FSM_RESP: begin
s_fsm_d = FSM_IDLE;
rib_slv.ready = s_rib_mst_ready_q;
rib_slv.rdata = s_rib_mst_rdata_q;
rib_slv.resp_err = s_rib_mst_resp_err_q;
end
default: s_fsm_d = FSM_IDLE;
endcase
end
dffr #(2) u_fsm_dffr (
clk_i,
rst_n_i,
s_fsm_d,
s_fsm_q
);
dffr #(1) u_rib_mstr_valid_dffr (
clk_i,
rst_n_i,
s_rib_mst_valid_d,
s_rib_mst_valid_q
);
dffr #(32) u_rib_mst_addr_dffr (
clk_i,
rst_n_i,
s_rib_mst_addr_d,
s_rib_mst_addr_q
);
dffr #(32) u_rib_mst_wdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_wdata_d,
s_rib_mst_wdata_q
);
dffr #(4) u_rib_mst_wstrb_dffr (
clk_i,
rst_n_i,
s_rib_mst_wstrb_d,
s_rib_mst_wstrb_q
);
dffr #(32) u_rib_mst_rdata_dffr (
clk_i,
rst_n_i,
s_rib_mst_rdata_d,
s_rib_mst_rdata_q
);
dffr #(1) u_rib_mst_ready_dffr (
clk_i,
rst_n_i,
s_rib_mst_ready_d,
s_rib_mst_ready_q
);
dffr #(1) u_rib_mst_resp_err_dffr (
clk_i,
rst_n_i,
s_rib_mst_resp_err_d,
s_rib_mst_resp_err_q
);
endmodule
rtl/mini/top/user_core_top.sv
+1 -1
View File
@@ -17,7 +17,7 @@ module user_core_top (
input logic [ 31:0] irq_i,
input logic [`USER_CORESEL_WIDTH-1:0] sel_i,
input logic [`USER_CORE_COUNT-1:0] core_reset_i,
soc_rib_if.master rib
rib_if.master rib
// verilog_format: on
);
tests/rtl/bus_fault_tb.sv
+23 -24
View File
@@ -11,10 +11,10 @@ module bus_fault_tb;
logic [ 1:0] fault_master_o;
logic [ 2:0] fault_code_o;
logic user_bus_idle_o;
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if mgmt_ribp ();
rib_if user_rib ();
rib_if dma_rib ();
rib_if rib ();
ribp_if apb_ribp ();
always #5 clk_i = ~clk_i;
@@ -24,7 +24,7 @@ module bus_fault_tb;
assign rib.rsp_valid = 1'b0;
assign rib.rdata = 32'hCAFE_BABE;
assign rib.resp_err = 1'b0;
assign rib.resp_code = `SOC_RIB_RESP_OK;
assign rib.resp_code = `RIB_RESP_OK;
assign rib.rsp_beat = '0;
assign rib.rsp_last = 1'b0;
assign apb_ribp.ready = 1'b1;
@@ -33,14 +33,13 @@ module bus_fault_tb;
bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_ribl (mgmt_ribl),
.mgmt_ribp (mgmt_ribp),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
@@ -56,22 +55,22 @@ module bus_fault_tb;
input logic reserved, input logic [2:0] expected_code);
begin
@(negedge clk_i);
mgmt_ribl.addr = address;
mgmt_ribl.wdata = 32'hA5A5_5A5A;
mgmt_ribl.wstrb = write_strobes;
mgmt_ribl.valid = 1'b1;
mgmt_ribp.addr = address;
mgmt_ribp.wdata = 32'hA5A5_5A5A;
mgmt_ribp.wstrb = write_strobes;
mgmt_ribp.valid = 1'b1;
while (!fault_valid_o) @(posedge clk_i);
if (fault_addr_o !== address || fault_wstrb_o !== write_strobes ||
fault_reserved_o !== reserved || fault_access_o || fault_code_o !== expected_code ||
rib.cmd_valid || apb_ribp.valid) begin
$fatal(1, "unexpected fault response for address %h", address);
end
while (!mgmt_ribl.ready) @(posedge clk_i);
if (mgmt_ribl.rdata !== 32'd0 || !mgmt_ribl.resp_err) begin
while (!mgmt_ribp.ready) @(posedge clk_i);
if (mgmt_ribp.rdata !== 32'd0 || !mgmt_ribp.resp_err) begin
$fatal(1, "fault response data must be zero");
end
@(negedge clk_i);
mgmt_ribl.valid = 1'b0;
mgmt_ribp.valid = 1'b0;
while (fault_valid_o) @(posedge clk_i);
end
endtask
@@ -81,7 +80,7 @@ module bus_fault_tb;
@(negedge clk_i);
user_rib.cmd_addr = address;
user_rib.cmd_write = |write_strobes;
user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
user_rib.cmd_len = `RIB_LEN_INCR1;
user_rib.cmd_valid = 1'b1;
while (!user_rib.cmd_ready) @(posedge clk_i);
@(negedge clk_i);
@@ -100,7 +99,7 @@ module bus_fault_tb;
$fatal(1, "user access was not denied locally");
end
if (user_rib.rdata !== 32'd0 || !user_rib.resp_err || !user_rib.rsp_last ||
user_rib.resp_code !== `SOC_RIB_RESP_PROTERR) begin
user_rib.resp_code !== `RIB_RESP_PROTERR) begin
$fatal(1, "denied user response data must be zero");
end
while (fault_valid_o) @(posedge clk_i);
@@ -108,14 +107,14 @@ module bus_fault_tb;
endtask
initial begin
mgmt_ribl.valid = 1'b0;
mgmt_ribl.addr = '0;
mgmt_ribl.wdata = '0;
mgmt_ribl.wstrb = '0;
mgmt_ribp.valid = 1'b0;
mgmt_ribp.addr = '0;
mgmt_ribp.wdata = '0;
mgmt_ribp.wstrb = '0;
user_rib.cmd_valid = 1'b0;
user_rib.cmd_addr = '0;
user_rib.cmd_write = 1'b0;
user_rib.cmd_len = `SOC_RIB_LEN_INCR1;
user_rib.cmd_len = `RIB_LEN_INCR1;
user_rib.w_valid = 1'b0;
user_rib.wdata = '0;
user_rib.wstrb = '0;
@@ -124,7 +123,7 @@ module bus_fault_tb;
dma_rib.cmd_valid = 1'b0;
dma_rib.cmd_addr = '0;
dma_rib.cmd_write = 1'b0;
dma_rib.cmd_len = `SOC_RIB_LEN_INCR1;
dma_rib.cmd_len = `RIB_LEN_INCR1;
dma_rib.w_valid = 1'b0;
dma_rib.wdata = '0;
dma_rib.wstrb = '0;
@@ -134,8 +133,8 @@ module bus_fault_tb;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
expect_fault(32'h1000_F000, 4'hF, 1'b1, `SOC_RIB_RESP_RESERVED);
expect_fault(32'hA000_0000, 4'h0, 1'b0, `SOC_RIB_RESP_DECERR);
expect_fault(32'h1000_F000, 4'hF, 1'b1, `RIB_RESP_RESERVED);
expect_fault(32'hA000_0000, 4'h0, 1'b0, `RIB_RESP_DECERR);
expect_user_denied(32'h1000_B000, 4'hF);
$display("bus fault responder test passed");
$finish;
tests/rtl/dma_error_tb.sv
+5 -5
View File
@@ -33,7 +33,7 @@ module dma_error_tb;
logic model_write_q = 1'b0;
logic model_error_q = 1'b0;
dma_hw_trg_if hw_trg ();
soc_rib_if rib ();
rib_if rib ();
always #5 clk_i = ~clk_i;
@@ -42,7 +42,7 @@ module dma_error_tb;
assign rib.rsp_valid = model_state_q == MODEL_RESP;
assign rib.rdata = 32'hA5A5_5A5A + model_beat_q;
assign rib.resp_err = model_error_q;
assign rib.resp_code = model_error_q ? `SOC_RIB_RESP_DECERR : `SOC_RIB_RESP_OK;
assign rib.resp_code = model_error_q ? `RIB_RESP_DECERR : `RIB_RESP_OK;
assign rib.rsp_beat = model_beat_q;
assign rib.rsp_last = model_write_q || model_error_q || (model_beat_q == model_len_q);
@@ -63,10 +63,10 @@ module dma_error_tb;
model_write_q <= rib.cmd_write;
model_error_q <= error_mode && !rib.cmd_write;
model_state_q <= rib.cmd_write ? MODEL_WDATA : MODEL_RESP;
if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && rib.cmd_write) begin
if (rib.cmd_len == `RIB_LEN_INCR4 && rib.cmd_write) begin
incr4_write_count <= incr4_write_count + 1;
end
if (rib.cmd_len == `SOC_RIB_LEN_INCR4 && !rib.cmd_write) begin
if (rib.cmd_len == `RIB_LEN_INCR4 && !rib.cmd_write) begin
incr4_read_count <= incr4_read_count + 1;
end
end
@@ -157,7 +157,7 @@ module dma_error_tb;
start_transfer();
wait (error_o);
@(negedge clk_i);
if (error_code_o !== `SOC_RIB_RESP_DECERR || error_addr_o !== srcaddr_i) begin
if (error_code_o !== `RIB_RESP_DECERR || error_addr_o !== srcaddr_i) begin
$fatal(1, "DMA error response was not propagated");
end
if (write_count != 1) begin
tests/rtl/soc_rib2ram_tb.sv → tests/rtl/rib2ram_tb.sv
+4 -4
View File
@@ -1,12 +1,12 @@
`timescale 1ns / 1ps
module soc_rib2ram_tb;
module rib2ram_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
logic [31:0] memory [0:31];
logic [31:0] expected [ 0:3];
integer index;
soc_rib_if rib ();
rib_if rib ();
ram_if ram ();
always #5 clk_i = ~clk_i;
@@ -19,7 +19,7 @@ module soc_rib2ram_tb;
if (ram.wstrb[3]) memory[ram.addr][31:24] <= ram.wdata[31:24];
end
soc_rib2ram u_dut (
rib2ram u_dut (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.rib (rib),
@@ -31,7 +31,7 @@ module soc_rib2ram_tb;
@(negedge clk_i);
rib.cmd_addr = 32'h3000_0000;
rib.cmd_write = write;
rib.cmd_len = `SOC_RIB_LEN_INCR4;
rib.cmd_len = `RIB_LEN_INCR4;
rib.cmd_valid = 1'b1;
while (!rib.cmd_ready) @(posedge clk_i);
@(negedge clk_i);
tests/rtl/rib_bus_tb.sv
+15 -16
View File
@@ -16,10 +16,10 @@ module rib_bus_tb;
logic fault_valid_o;
logic [2:0] fault_code_o;
logic user_bus_idle_o;
soc_ribl_if mgmt_ribl ();
soc_rib_if user_rib ();
soc_rib_if dma_rib ();
soc_rib_if rib ();
ribp_if mgmt_ribp ();
rib_if user_rib ();
rib_if dma_rib ();
rib_if rib ();
ribp_if apb_ribp ();
always #5 clk_i = ~clk_i;
@@ -30,7 +30,7 @@ module rib_bus_tb;
assign rib.rsp_valid = target_state_q == TARGET_RESP;
assign rib.rdata = 32'hCAFE_0000 + target_beat_q;
assign rib.resp_err = 1'b0;
assign rib.resp_code = `SOC_RIB_RESP_OK;
assign rib.resp_code = `RIB_RESP_OK;
assign rib.rsp_beat = target_beat_q;
assign rib.rsp_last = target_beat_q == target_len_q;
@@ -63,14 +63,13 @@ module rib_bus_tb;
bus u_bus (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mgmt_ribl (mgmt_ribl),
.mgmt_ribp (mgmt_ribp),
.user_rib (user_rib),
.dma_rib (dma_rib),
.user_bus_enable_i(1'b1),
.user_bus_idle_o (user_bus_idle_o),
.rib (rib),
.apb_ribp (apb_ribp),
.apb_resp_err_i (1'b0),
.perf_enable_i (1'b0),
.perf_clear_i (1'b0),
.fault_valid_o (fault_valid_o),
@@ -109,7 +108,7 @@ module rib_bus_tb;
$fatal(1, "unexpected response status for %h", address);
end
if (expect_error) begin
if (dma_rib.resp_code !== `SOC_RIB_RESP_BURSTERR || !dma_rib.rsp_last) begin
if (dma_rib.resp_code !== `RIB_RESP_BURSTERR || !dma_rib.rsp_last) begin
$fatal(1, "illegal burst did not return terminal BURSTERR");
end
response_count = length + 1;
@@ -130,10 +129,10 @@ module rib_bus_tb;
endtask
initial begin
mgmt_ribl.valid = 1'b0;
mgmt_ribl.addr = '0;
mgmt_ribl.wdata = '0;
mgmt_ribl.wstrb = '0;
mgmt_ribp.valid = 1'b0;
mgmt_ribp.addr = '0;
mgmt_ribp.wdata = '0;
mgmt_ribp.wstrb = '0;
user_rib.cmd_valid = 1'b0;
user_rib.cmd_addr = '0;
user_rib.cmd_write = 1'b0;
@@ -156,13 +155,13 @@ module rib_bus_tb;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
issue_read(32'h3800_1000, `SOC_RIB_LEN_INCR4, 1'b0);
issue_read(32'h3800_1000, `RIB_LEN_INCR4, 1'b0);
if (rib_command_count != 1) begin
$fatal(1, "INCR4 was split before reaching the burst RIB target");
end
issue_read(32'h3800_1004, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h1000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h2000_0000, `SOC_RIB_LEN_INCR4, 1'b1);
issue_read(32'h3800_1004, `RIB_LEN_INCR4, 1'b1);
issue_read(32'h1000_0000, `RIB_LEN_INCR4, 1'b1);
issue_read(32'h2000_0000, `RIB_LEN_INCR4, 1'b1);
issue_read(32'h3800_1000, 2'd2, 1'b1);
if (rib_command_count != 1 || apb_ribp.valid) begin
$fatal(1, "illegal burst reached a downstream target");
tests/rtl/soc_topology_ribp_tb.sv → tests/rtl/ribp_topology_tb.sv
+45 -3
View File
@@ -2,13 +2,13 @@
`include "mmap_define.svh"
module soc_topology_ribp_tb;
module ribp_topology_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
ribp_if ribp ();
`include "soc_ribp_interfaces.svh"
`include "soc_ribp_routes.svh"
`include "ribp_interfaces.svh"
`include "ribp_routes.svh"
always #5 clk_i = ~clk_i;
@@ -53,6 +53,26 @@ module soc_topology_ribp_tb;
end
endtask
task automatic expect_error_route(input logic [31:0] address, input integer slot);
begin
@(negedge clk_i);
ribp.addr = address;
ribp.valid = 1'b1;
#1;
if (s_slv_sel_d !== (18'd1 << slot)) begin
$fatal(1, "unexpected error target slot for %h", address);
end
@(posedge clk_i);
#1;
if (!ribp.ready || !ribp.resp_err) begin
$fatal(1, "error response was not propagated for %h", address);
end
@(negedge clk_i);
ribp.valid = 1'b0;
@(posedge clk_i);
end
endtask
initial begin
ribp.valid = 1'b0;
ribp.addr = '0;
@@ -97,6 +117,25 @@ module soc_topology_ribp_tb;
u_opipsram_ribp_if.rdata = 32'h0F0F_0F0F;
u_i2c1_ribp_if.rdata = 32'h1234_5678;
u_uart_ribp_if.resp_err = 1'b0;
u_gpio_ribp_if.resp_err = 1'b0;
u_tim0_ribp_if.resp_err = 1'b0;
u_tim1_ribp_if.resp_err = 1'b0;
u_psram_ribp_if.resp_err = 1'b0;
u_spisd_ribp_if.resp_err = 1'b0;
u_i2c0_ribp_if.resp_err = 1'b0;
u_i2s_ribp_if.resp_err = 1'b0;
u_onewire_ribp_if.resp_err = 1'b0;
u_xpi_ribp_if.resp_err = 1'b0;
u_dma_ribp_if.resp_err = 1'b0;
u_sysctrl_ribp_if.resp_err = 1'b0;
u_clint_ribp_if.resp_err = 1'b0;
u_sdram_ribp_if.resp_err = 1'b0;
u_dvp_ribp_if.resp_err = 1'b0;
u_sdio_ribp_if.resp_err = 1'b0;
u_opipsram_ribp_if.resp_err = 1'b0;
u_i2c1_ribp_if.resp_err = 1'b0;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
@@ -105,6 +144,9 @@ module soc_topology_ribp_tb;
expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
expect_route(`SOC_ADDR_RIBP_I2C1_BASE, 17, 32'h1234_5678);
expect_disabled(`SOC_ADDR_RIBP_SDIO_BASE);
u_gpio_ribp_if.resp_err = 1'b1;
expect_error_route(`SOC_ADDR_RIBP_GPIO_BASE, 1);
u_gpio_ribp_if.resp_err = 1'b0;
$display("SoC topology RIBP routing test passed");
$finish;
tests/rtl/sysctrl_fault_tb.sv
+4 -4
View File
@@ -63,7 +63,7 @@ module sysctrl_fault_tb;
sysctrl.user_bus_idle_i = 1'b1;
sysctrl.fault_access_i = 1'b0;
sysctrl.fault_master_i = '0;
sysctrl.fault_code_i = `SOC_RIB_RESP_RESERVED;
sysctrl.fault_code_i = `RIB_RESP_RESERVED;
sysctrl.perf_mgmt_wait_i = 64'd11;
sysctrl.perf_user_wait_i = 64'd12;
sysctrl.perf_dma_wait_i = 64'd13;
@@ -98,10 +98,10 @@ module sysctrl_fault_tb;
read_register(32'h1000_B018, read_data);
if (read_data !== 32'h0000_0001) $fatal(1, "fault count was not incremented");
read_register(32'h1000_B02C, read_data);
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
@(negedge clk_i);
sysctrl.fault_code_i = `SOC_RIB_RESP_DECERR;
sysctrl.fault_code_i = `RIB_RESP_DECERR;
fault_valid_i = 1'b1;
fault_addr_i = 32'hA000_0000;
fault_wstrb_i = 4'h0;
@@ -113,7 +113,7 @@ module sysctrl_fault_tb;
read_register(32'h1000_B018, read_data);
if (read_data !== 32'h0000_0002) $fatal(1, "later fault did not increment count");
read_register(32'h1000_B02C, read_data);
if (read_data !== `SOC_RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
write_register(32'h1000_B010, 32'h0000_0001);
read_register(32'h1000_B010, read_data);
tests/test_dma.py
+1 -2
View File
@@ -40,8 +40,7 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) -
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/mini/top'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
tests/test_memory_map.py
+5 -8
View File
@@ -114,14 +114,13 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
str(ROOT / "rtl/mini/top/ribp2rib.sv"),
str(ROOT / "rtl/mini/top/rib2ribp.sv"),
str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/rib2ram.sv"),
str(ROOT / "rtl/mini/top/bus.sv"),
str(ROOT / "tests/rtl/bus_fault_tb.sv"),
"",
@@ -173,7 +172,6 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
@@ -222,7 +220,6 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"),
tests/test_rib.py
+12 -13
View File
@@ -41,14 +41,13 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_ribl_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_ribl2rib.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ribp.sv"),
str(ROOT / "rtl/mini/top/soc_rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
str(ROOT / "rtl/mini/top/ribp2rib.sv"),
str(ROOT / "rtl/mini/top/rib2ribp.sv"),
str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
str(ROOT / "rtl/mini/top/rib2ram.sv"),
str(ROOT / "rtl/mini/top/bus.sv"),
str(ROOT / "tests/rtl/rib_bus_tb.sv"),
"",
@@ -83,7 +82,7 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
if iverilog is None or vvp is None:
return
source_list = tmp_path / "soc_rib2ram.fl"
source_list = tmp_path / "rib2ram.fl"
source_list.write_text(
"\n".join(
[
@@ -91,17 +90,17 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
f"+incdir+{ROOT / 'rtl/mini/top'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
str(ROOT / "rtl/mini/top/soc_rib_if.sv"),
str(ROOT / "rtl/mini/top/rib_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
str(ROOT / "rtl/mini/top/soc_rib2ram.sv"),
str(ROOT / "tests/rtl/soc_rib2ram_tb.sv"),
str(ROOT / "rtl/mini/top/rib2ram.sv"),
str(ROOT / "tests/rtl/rib2ram_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "soc_rib2ram_tb.v"
converted = tmp_path / "rib2ram_tb.v"
subprocess.run(
[
sys.executable,
@@ -113,9 +112,9 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
],
check=True,
)
simulation = tmp_path / "soc_rib2ram_tb"
simulation = tmp_path / "rib2ram_tb"
subprocess.run(
[iverilog, "-g2012", "-s", "soc_rib2ram_tb", "-o", str(simulation), str(converted)],
[iverilog, "-g2012", "-s", "rib2ram_tb", "-o", str(simulation), str(converted)],
check=True,
)
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
tests/test_script_tools.py
+5 -5
View File
@@ -210,11 +210,11 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non
gpio_user = parse_filelists([gpio_user_filelist], require_files=False)
assert "+define+SV_ASSRT_DISABLE" in bus.defines
assert ROOT / "rtl/mini/top/bus.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_if.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_ribl2rib.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib_error_slave.sv" in bus.files
assert ROOT / "rtl/mini/top/rib_if.sv" in bus.files
assert ROOT / "rtl/mini/top/ribp2rib.sv" in bus.files
assert ROOT / "rtl/mini/top/rib_error_slave.sv" in bus.files
assert ROOT / "rtl/mini/formal/bus_formal.sv" in bus.files
assert ROOT / "rtl/mini/top/soc_rib2ribp.sv" in rib_adapter.files
assert ROOT / "rtl/mini/top/rib2ribp.sv" in rib_adapter.files
assert ROOT / "rtl/mini/formal/rib_adapter_formal.sv" in rib_adapter.files
assert ROOT / "rtl/ip/ribp/interconnect/ribp2apb.sv" in ribp2apb.files
assert ROOT / "rtl/mini/formal/ribp2apb_formal.sv" in ribp2apb.files
@@ -654,7 +654,7 @@ def test_management_core_selection_is_limited_to_hazard3_and_picorv32() -> None:
assert "DEF_LIST += +define+CORE_$(CORE)" in makefile
assert "`ifdef CORE_PICORV32" in wrapper
assert "`elsif CORE_HAZARD3" in wrapper
assert "ahbl2soc_ribl u_ahbl2soc_rib" in wrapper
assert "ahbl2ribp u_ahbl2ribp" in wrapper
assert ".RESET_VECTOR (`SOC_CPU_RESET_ADDR)" in wrapper
tests/test_soc_topology.py
+13 -12
View File
@@ -57,8 +57,8 @@ def write_invalid_topology(tmp_path: Path, document: dict[str, object]) -> Path:
def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -> None:
generate(tmp_path)
interfaces = (tmp_path / "rtl/soc_ribp_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/soc_ribp_routes.svh").read_text(encoding="utf-8")
interfaces = (tmp_path / "rtl/ribp_interfaces.svh").read_text(encoding="utf-8")
routes = (tmp_path / "rtl/ribp_routes.svh").read_text(encoding="utf-8")
gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
@@ -67,7 +67,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
rib_irq = (tmp_path / "rtl/soc_ribp_irq_bindings.svh").read_text(encoding="utf-8")
rib_irq = (tmp_path / "rtl/ribp_irq_bindings.svh").read_text(encoding="utf-8")
apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
@@ -77,6 +77,8 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
assert "nmi_if" not in interfaces
assert "soc_nmi" not in interfaces
assert "assign s_slv_sel_d[17] = u_i2c1_ribp_if.valid;" in routes
assert "assign s_slv_resp_err[17] = u_i2c1_ribp_if.resp_err;" in routes
assert "assign ribp.resp_err = |(s_slv_sel_q & s_slv_ready & s_slv_resp_err);" in routes
assert "assign s_xpi_region_sel[1] = (ribp.addr <= `SOC_ADDR_FLASH_END);" in routes
assert "assign u_sdio_ribp_if.valid = 1'b0;" in routes
assert gpio.count("// GPIO") == 64
@@ -87,10 +89,9 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
assert "assign tmr.paddr = ribp.addr;" in apb_routes
assert "({32{s_psel_q[8]}} & tmr.prdata)" in apb_response
assert "localparam int NSLV = 10;" in apb_declarations
assert fabric.count("soc_ribl_if u_") == 1
assert fabric.count("soc_rib_if u_") == 3
assert fabric.count("ribp_if u_") == 1
assert ".mgmt_ribl(u_mgmt_ribl_if)" in bus_fabric
assert fabric.count("ribp_if u_") == 2
assert fabric.count("rib_if u_") == 3
assert ".mgmt_ribp(u_mgmt_ribp_if)" in bus_fabric
assert ".user_rib(u_user_rib_if)" in bus_fabric
assert ".apb_ribp(u_apb_ribp_if)" in bus_fabric
assert ".rib(u_rib_if)" in bus_fabric
@@ -317,7 +318,7 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
topology_output = tmp_path / "topology"
generate(topology_output)
source_list = tmp_path / "soc_topology_ribp.fl"
source_list = tmp_path / "ribp_topology.fl"
source_list.write_text(
"\n".join(
[
@@ -327,13 +328,13 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "tests/rtl/soc_topology_ribp_tb.sv"),
str(ROOT / "tests/rtl/ribp_topology_tb.sv"),
"",
]
),
encoding="utf-8",
)
converted = tmp_path / "soc_topology_ribp_tb.v"
converted = tmp_path / "ribp_topology_tb.v"
subprocess.run(
[
sys.executable,
@@ -345,13 +346,13 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa
],
check=True,
)
simulation = tmp_path / "soc_topology_ribp_tb"
simulation = tmp_path / "ribp_topology_tb"
subprocess.run(
[
iverilog,
"-g2012",
"-s",
"soc_topology_ribp_tb",
"ribp_topology_tb",
"-o",
str(simulation),
str(converted),
tests/test_user_extensions.py
+1 -1
View File
@@ -48,7 +48,7 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
assert core.count("soc_rib_if u_user_") == 6
assert core.count("rib_if u_user_") == 6
assert core.count("ribp_if u_user_") == 6
assert core.count("ribp2rib #(") == 6
assert core.count(".SYNC_RESET(1'b1)") == 2